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Data Structures</h2></td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_traf_gen___c_ram_cmd.html">XTrafGen_CRamCmd</a></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_traf_gen___p_ram_cmd.html">XTrafGen_PRamCmd</a></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_traf_gen___cmd.html">XTrafGen_Cmd</a></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_traf_gen___cmd_entry.html">XTrafGen_CmdEntry</a></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_traf_gen___config.html">XTrafGen_Config</a></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_traf_gen___cmd_info.html">XTrafGen_CmdInfo</a></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_traf_gen.html">XTrafGen</a></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:gaa852fb64cd7119a1feeb5715a794d79d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#gaa852fb64cd7119a1feeb5715a794d79d">XTrafGen_GetCmdInfo</a>(InstancePtr)&#160;&#160;&#160;(&amp;((InstancePtr)-&gt;CmdInfo))</td></tr>
<tr class="separator:gaa852fb64cd7119a1feeb5715a794d79d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4d79e5e5aab48b68ee266961b89da00c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga4d79e5e5aab48b68ee266961b89da00c">XTrafGen_ReadCoreRevision</a>(InstancePtr)</td></tr>
<tr class="separator:ga4d79e5e5aab48b68ee266961b89da00c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1146dfb17253668f42cd6b2f679552cc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga1146dfb17253668f42cd6b2f679552cc">XTrafGen_ReadIdWidth</a>(InstancePtr)</td></tr>
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<tr class="memitem:gaf55f0066544c5ca956f2775e2927851d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#gaf55f0066544c5ca956f2775e2927851d">XTrafGen_StartMasterLogic</a>(InstancePtr)</td></tr>
<tr class="separator:gaf55f0066544c5ca956f2775e2927851d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga067b6b58a33f91e8fb345224a12fd713"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga067b6b58a33f91e8fb345224a12fd713">XTrafGen_IsMasterLogicDone</a>(InstancePtr)</td></tr>
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<tr class="memitem:ga7ae20ec6a0531e09e0723905c20bb572"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga7ae20ec6a0531e09e0723905c20bb572">XTrafGen_LoopEnable</a>(InstancePtr)</td></tr>
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<tr class="memitem:gad1d6d337106b8d03118d625159a93cf4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#gad1d6d337106b8d03118d625159a93cf4">XTrafGen_LoopDisable</a>(InstancePtr)</td></tr>
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<tr class="memitem:ga46f61a2e9582be8d787633db33637947"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga46f61a2e9582be8d787633db33637947">XTrafGen_WriteSlaveControlReg</a>(InstancePtr,  Value)</td></tr>
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<tr class="memitem:ga1e86bf806f4ae36b671eef5f97b0b822"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga1e86bf806f4ae36b671eef5f97b0b822">XTrafGen_CheckforMasterComplete</a>(InstancePtr)</td></tr>
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<tr class="memitem:ga6e6159d969c5f451f429b9d8ec4a42f8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga6e6159d969c5f451f429b9d8ec4a42f8">XTrafGen_EnableErrors</a>(InstancePtr,  Mask)</td></tr>
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<tr class="memitem:ga154f34818edeb0858c445690fa4f8670"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga154f34818edeb0858c445690fa4f8670">XTrafGen_MasterErrIntrEnable</a>(InstancePtr)                                      </td></tr>
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<tr class="memitem:gab224de7e1fd0dcc9dc2627b625f81424"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#gab224de7e1fd0dcc9dc2627b625f81424">XTrafGen_MasterErrIntrDisable</a>(InstancePtr)                                      </td></tr>
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<tr class="memitem:ga298a1b459b4552cb79b4a2da8d3a1845"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga298a1b459b4552cb79b4a2da8d3a1845">XTrafGen_SlaveErrIntrEnable</a>(InstancePtr)                                      </td></tr>
<tr class="separator:ga298a1b459b4552cb79b4a2da8d3a1845"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa4b8bcf25ed401a3debc9665db06dfef"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#gaa4b8bcf25ed401a3debc9665db06dfef">XTrafGen_SlaveErrIntrDisable</a>(InstancePtr)</td></tr>
<tr class="separator:gaa4b8bcf25ed401a3debc9665db06dfef"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad072536408b0e73e38978c57e0002c79"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#gad072536408b0e73e38978c57e0002c79">XTrafGen_ReadConfigStatus</a>(InstancePtr)                                      </td></tr>
<tr class="separator:gad072536408b0e73e38978c57e0002c79"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga21218c919ca08e948a557334a8f1ba95"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga21218c919ca08e948a557334a8f1ba95">XTrafGen_StaticEnable</a>(InstancePtr)</td></tr>
<tr class="separator:ga21218c919ca08e948a557334a8f1ba95"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab54737e40a38ba5316b487a045568b11"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#gab54737e40a38ba5316b487a045568b11">XTrafGen_StaticDisable</a>(InstancePtr)</td></tr>
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<tr class="memitem:ga37b20b8af9dbdef32b778e28b28beebb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga37b20b8af9dbdef32b778e28b28beebb">XTrafGen_StaticVersion</a>(InstancePtr)</td></tr>
<tr class="separator:ga37b20b8af9dbdef32b778e28b28beebb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga67433007f5c7594c7595fb71e85e938f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga67433007f5c7594c7595fb71e85e938f">XTrafGen_SetStaticBurstLen</a>(InstancePtr,  Value)</td></tr>
<tr class="separator:ga67433007f5c7594c7595fb71e85e938f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaedebd87b7d6727d97552da64fbb16d69"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#gaedebd87b7d6727d97552da64fbb16d69">XTrafGen_GetStaticBurstLen</a>(InstancePtr)</td></tr>
<tr class="separator:gaedebd87b7d6727d97552da64fbb16d69"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7b1b98f0a7cb8a9dca62ecadbc1d6d42"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga7b1b98f0a7cb8a9dca62ecadbc1d6d42">XTrafGen_GetStaticTransferDone</a>(InstancePtr)</td></tr>
<tr class="separator:ga7b1b98f0a7cb8a9dca62ecadbc1d6d42"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacba2dd56bfff034a966b81a2103a6bb4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#gacba2dd56bfff034a966b81a2103a6bb4">XTrafGen_SetStaticTransferDone</a>(InstancePtr)   	</td></tr>
<tr class="separator:gacba2dd56bfff034a966b81a2103a6bb4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga865f2e2498c2c50c43b5f9c1abfc54e2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga865f2e2498c2c50c43b5f9c1abfc54e2">XTrafGen_IsStaticTransferDone</a>(InstancePtr)</td></tr>
<tr class="separator:ga865f2e2498c2c50c43b5f9c1abfc54e2"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<tr class="separator:gaadc216c9d0077b5906e2b07029b8877a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9254cbaa150c31ba61e141e3cdc9a4c7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga9254cbaa150c31ba61e141e3cdc9a4c7">XTrafGen_StreamDisable</a>(InstancePtr)</td></tr>
<tr class="separator:ga9254cbaa150c31ba61e141e3cdc9a4c7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga97bb49960ada1e396862580a5e41755e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga97bb49960ada1e396862580a5e41755e">XTrafGen_StreamVersion</a>(InstancePtr)</td></tr>
<tr class="separator:ga97bb49960ada1e396862580a5e41755e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae7e5d3e4f6de43f247a5f52dbade8deb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#gae7e5d3e4f6de43f247a5f52dbade8deb">XTrafGen_SetStreamingTransLen</a>(InstancePtr,  Value)</td></tr>
<tr class="separator:gae7e5d3e4f6de43f247a5f52dbade8deb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf17c0eadf5962f5dd8ba970b77dd12e6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#gaf17c0eadf5962f5dd8ba970b77dd12e6">XTrafGen_GetStreamingTransLen</a>(InstancePtr)</td></tr>
<tr class="separator:gaf17c0eadf5962f5dd8ba970b77dd12e6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9628f47e6f85fc3dba9f55c4b28b2e69"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga9628f47e6f85fc3dba9f55c4b28b2e69">XTrafGen_GetStreamingTransCnt</a>(InstancePtr)</td></tr>
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<tr class="memitem:gaab0a135f1ad92788eeb768cfe26b74b3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#gaab0a135f1ad92788eeb768cfe26b74b3">XTrafGen_SetStreamingRandomLen</a>(InstancePtr,  Value)</td></tr>
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<tr class="memitem:ga01e30039d0fef72f9bf3d51ff437d9d2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga01e30039d0fef72f9bf3d51ff437d9d2">XTrafGen_GetStreamingProgDelay</a>(InstancePtr)</td></tr>
<tr class="separator:ga01e30039d0fef72f9bf3d51ff437d9d2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga90d0e4161092c15a1ca821f97cdd7a4b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga90d0e4161092c15a1ca821f97cdd7a4b">XTrafGen_SetStreamingTransCnt</a>(InstancePtr,  Value)</td></tr>
<tr class="separator:ga90d0e4161092c15a1ca821f97cdd7a4b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3beeeec32649b7df9c049a6b08daa55a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga3beeeec32649b7df9c049a6b08daa55a">XTrafGen_SetStreamingProgDelay</a>(InstancePtr,  Value)</td></tr>
<tr class="separator:ga3beeeec32649b7df9c049a6b08daa55a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae5372945bcdfa008f7daf48f97edbd7f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#gae5372945bcdfa008f7daf48f97edbd7f">XTrafGen_SetStreamingTdestPort</a>(InstancePtr,  Value)</td></tr>
<tr class="separator:gae5372945bcdfa008f7daf48f97edbd7f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaee4aa3d826f692264c3735a00c29aa47"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#gaee4aa3d826f692264c3735a00c29aa47">XTrafGen_SetStreamingTransferDone</a>(InstancePtr)  </td></tr>
<tr class="separator:gaee4aa3d826f692264c3735a00c29aa47"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0ff0fea3c2324dbd0c6edc5efd5ba709"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga0ff0fea3c2324dbd0c6edc5efd5ba709">XTrafGen_IsStreamingTransferDone</a>(InstancePtr)</td></tr>
<tr class="separator:ga0ff0fea3c2324dbd0c6edc5efd5ba709"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5481f14f30231fcf80dafa2b77f6e8a3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga5481f14f30231fcf80dafa2b77f6e8a3">XTrafGen_ResetStreamingRandomLen</a>(InstancePtr)</td></tr>
<tr class="separator:ga5481f14f30231fcf80dafa2b77f6e8a3"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="typedef-members"></a>
Typedefs</h2></td></tr>
<tr class="memitem:ga9000b8a48f4981622f182d63c93984cd"><td class="memItemLeft" align="right" valign="top">typedef struct <a class="el" href="struct_x_traf_gen___c_ram_cmd.html">XTrafGen_CRamCmd</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga9000b8a48f4981622f182d63c93984cd">XTrafGen_CRamCmd</a></td></tr>
<tr class="separator:ga9000b8a48f4981622f182d63c93984cd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga10db2410ee506abab9d3d70f7168dde9"><td class="memItemLeft" align="right" valign="top">typedef struct <a class="el" href="struct_x_traf_gen___p_ram_cmd.html">XTrafGen_PRamCmd</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga10db2410ee506abab9d3d70f7168dde9">XTrafGen_PRamCmd</a></td></tr>
<tr class="separator:ga10db2410ee506abab9d3d70f7168dde9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga94123d18434c2c1ac774e8f65370f7dd"><td class="memItemLeft" align="right" valign="top">typedef struct <a class="el" href="struct_x_traf_gen___cmd.html">XTrafGen_Cmd</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga94123d18434c2c1ac774e8f65370f7dd">XTrafGen_Cmd</a></td></tr>
<tr class="separator:ga94123d18434c2c1ac774e8f65370f7dd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga470be5d4f63cbe0f7fb87b11a7683fc1"><td class="memItemLeft" align="right" valign="top">typedef struct <a class="el" href="struct_x_traf_gen___cmd_entry.html">XTrafGen_CmdEntry</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga470be5d4f63cbe0f7fb87b11a7683fc1">XTrafGen_CmdEntry</a></td></tr>
<tr class="separator:ga470be5d4f63cbe0f7fb87b11a7683fc1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0ba0ed4084853050ccea879abe7c8a19"><td class="memItemLeft" align="right" valign="top">typedef struct <a class="el" href="struct_x_traf_gen___config.html">XTrafGen_Config</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga0ba0ed4084853050ccea879abe7c8a19">XTrafGen_Config</a></td></tr>
<tr class="separator:ga0ba0ed4084853050ccea879abe7c8a19"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabc2346365e8d4e0e606633d4f5eda16a"><td class="memItemLeft" align="right" valign="top">typedef struct <a class="el" href="struct_x_traf_gen___cmd_info.html">XTrafGen_CmdInfo</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#gabc2346365e8d4e0e606633d4f5eda16a">XTrafGen_CmdInfo</a></td></tr>
<tr class="separator:gabc2346365e8d4e0e606633d4f5eda16a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1e9571461b3c74299c15293343a21900"><td class="memItemLeft" align="right" valign="top">typedef struct <a class="el" href="struct_x_traf_gen.html">XTrafGen</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga1e9571461b3c74299c15293343a21900">XTrafGen</a></td></tr>
<tr class="separator:ga1e9571461b3c74299c15293343a21900"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:ga4d40f6d5551836dab49e0d22e8d5e1eb"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga4d40f6d5551836dab49e0d22e8d5e1eb">XTrafGen_CfgInitialize</a> (<a class="el" href="struct_x_traf_gen.html">XTrafGen</a> *InstancePtr, <a class="el" href="struct_x_traf_gen___config.html">XTrafGen_Config</a> *Config, UINTPTR EffectiveAddress)</td></tr>
<tr class="separator:ga4d40f6d5551836dab49e0d22e8d5e1eb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga39eaea669c1ff2df58e54c002b43f854"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga39eaea669c1ff2df58e54c002b43f854">XTrafGen_AddCommand</a> (<a class="el" href="struct_x_traf_gen.html">XTrafGen</a> *InstancePtr, <a class="el" href="struct_x_traf_gen___cmd.html">XTrafGen_Cmd</a> *CmdPtr)</td></tr>
<tr class="separator:ga39eaea669c1ff2df58e54c002b43f854"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga262d850cbfc5b0495fbc2d84334a1fba"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga262d850cbfc5b0495fbc2d84334a1fba">XTrafGen_GetLastValidIndex</a> (<a class="el" href="struct_x_traf_gen.html">XTrafGen</a> *InstancePtr, u32 RdWrFlag)</td></tr>
<tr class="separator:ga262d850cbfc5b0495fbc2d84334a1fba"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga14377a8884e99ce01c0c76128c939c49"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga14377a8884e99ce01c0c76128c939c49">XTrafGen_WriteCmdsToHw</a> (<a class="el" href="struct_x_traf_gen.html">XTrafGen</a> *InstancePtr)</td></tr>
<tr class="separator:ga14377a8884e99ce01c0c76128c939c49"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga539d4976ad3ace9e15d993e2b18143a0"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga539d4976ad3ace9e15d993e2b18143a0">XTrafGen_EraseAllCommands</a> (<a class="el" href="struct_x_traf_gen.html">XTrafGen</a> *InstancePtr)</td></tr>
<tr class="separator:ga539d4976ad3ace9e15d993e2b18143a0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaaea625b89454268bbbe7f93e309141c4"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#gaaea625b89454268bbbe7f93e309141c4">XTrafGen_AccessMasterRam</a> (<a class="el" href="struct_x_traf_gen.html">XTrafGen</a> *InstancePtr, u32 Offset, int Length, u8 RdWrFlag, u32 *Data)</td></tr>
<tr class="separator:gaaea625b89454268bbbe7f93e309141c4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad9654a81e902175a963c83edb0c37144"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#gad9654a81e902175a963c83edb0c37144">XTrafGen_PrintCmds</a> (<a class="el" href="struct_x_traf_gen.html">XTrafGen</a> *InstancePtr)</td></tr>
<tr class="separator:gad9654a81e902175a963c83edb0c37144"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacbf906e378777e17e7d68729315993ec"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_traf_gen___config.html">XTrafGen_Config</a> *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#gacbf906e378777e17e7d68729315993ec">XTrafGen_LookupConfig</a> (u32 DeviceId)</td></tr>
<tr class="separator:gacbf906e378777e17e7d68729315993ec"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
Device registers</h2></td></tr>
<tr class="memitem:gafee2ca23e3fc2ed4964740ba69dde023"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#gafee2ca23e3fc2ed4964740ba69dde023">XTG_STATIC_CNTL_OFFSET</a>&#160;&#160;&#160;0x60</td></tr>
<tr class="separator:gafee2ca23e3fc2ed4964740ba69dde023"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<h2 class="groupheader">Macro Definition Documentation</h2>
<a class="anchor" id="gaefe8b2fd0fb990e5cfa429c8b49b3162"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define MAX_NUM_ENTRIES&#160;&#160;&#160;256</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>

<p>Number of command entries per region. </p>

<p>Referenced by <a class="el" href="group__trafgen__v3__2.html#ga39eaea669c1ff2df58e54c002b43f854">XTrafGen_AddCommand()</a>, <a class="el" href="group__trafgen__v3__2.html#ga539d4976ad3ace9e15d993e2b18143a0">XTrafGen_EraseAllCommands()</a>, and <a class="el" href="group__trafgen__v3__2.html#gad9654a81e902175a963c83edb0c37144">XTrafGen_PrintCmds()</a>.</p>

</div>
</div>
<a class="anchor" id="ga622293b32ccc06f19e7f568ba80a2390"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define NUM_BLOCKS&#160;&#160;&#160;2</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>

<p>Number of Read and write regions. </p>

<p>Referenced by <a class="el" href="group__trafgen__v3__2.html#ga539d4976ad3ace9e15d993e2b18143a0">XTrafGen_EraseAllCommands()</a>, and <a class="el" href="group__trafgen__v3__2.html#ga14377a8884e99ce01c0c76128c939c49">XTrafGen_WriteCmdsToHw()</a>.</p>

</div>
</div>
<a class="anchor" id="gadf7e15dfd4ecd23278ff780bf4369058"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_CFG_STS_OFFSET&#160;&#160;&#160;0x14</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen__hw_8h.html">xtrafgen_hw.h</a>&gt;</code></p>

<p>Config Status. </p>

</div>
</div>
<a class="anchor" id="gae6768580423b3cbb32e1822433634463"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_CMD_RAM_BLOCK_SIZE&#160;&#160;&#160;0x1000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>

<p>Cmd RAM Block Size (4KB) </p>

</div>
</div>
<a class="anchor" id="ga6fd650735d7eb15cc3cd76679f8b7894"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_COMMAND_RAM_MSB_OFFSET&#160;&#160;&#160;0xa000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen__hw_8h.html">xtrafgen_hw.h</a>&gt;</code></p>

<p>Command RAM MSB Offset. </p>

</div>
</div>
<a class="anchor" id="ga1b4f5daeb95b5827db0760c1c0dc13e5"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_COMMAND_RAM_OFFSET&#160;&#160;&#160;0x8000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen__hw_8h.html">xtrafgen_hw.h</a>&gt;</code></p>

<p>Command RAM Offset. </p>

</div>
</div>
<a class="anchor" id="ga917ddd8cff98a1e520664e21bffc3b58"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_COMMAND_RAM_SIZE&#160;&#160;&#160;0x2000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>

<p>Command RAM (8KB) </p>

</div>
</div>
<a class="anchor" id="gafdb598343bdb0bf2c6c5d29f8258f692"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_ERR_ALL_ERR_MASK&#160;&#160;&#160;0x001F0003</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen__hw_8h.html">xtrafgen_hw.h</a>&gt;</code></p>

<p>All Errors Mask. </p>

</div>
</div>
<a class="anchor" id="ga7a6d5a7be767a9e7de7e441416584ba5"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_ERR_ALL_MSTERR_MASK&#160;&#160;&#160;0x001F0000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen__hw_8h.html">xtrafgen_hw.h</a>&gt;</code></p>

<p>Master Errors Mask. </p>

</div>
</div>
<a class="anchor" id="ga9c335dd2550acee9495bfd72fc7e3e4d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_ERR_ALL_SLVERR_MASK&#160;&#160;&#160;0x00000003</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen__hw_8h.html">xtrafgen_hw.h</a>&gt;</code></p>

<p>Slave Errors Mask. </p>

</div>
</div>
<a class="anchor" id="ga54f00a5d7ea7acb0a8917b79f6aeeb57"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_ERR_EN_OFFSET&#160;&#160;&#160;0x0C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen__hw_8h.html">xtrafgen_hw.h</a>&gt;</code></p>

<p>Error Enable. </p>

</div>
</div>
<a class="anchor" id="ga5cefaef257524651df762212be509765"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_ERR_MSTCMP_MASK&#160;&#160;&#160;0x80000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen__hw_8h.html">xtrafgen_hw.h</a>&gt;</code></p>

<p>Master Complete Mask. </p>

</div>
</div>
<a class="anchor" id="ga40d2ed4ab43a43d5911d28db379536f9"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_ERR_RERRSP_MASK&#160;&#160;&#160;0x00020000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen__hw_8h.html">xtrafgen_hw.h</a>&gt;</code></p>

<p>MR Invalid RESP Mask. </p>

</div>
</div>
<a class="anchor" id="gaf6d50ea72391faca9e9bf364ac16abbe"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_ERR_RIDER_MASK&#160;&#160;&#160;0x00100000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen__hw_8h.html">xtrafgen_hw.h</a>&gt;</code></p>

<p>Master Invalid RVALID Mask. </p>

</div>
</div>
<a class="anchor" id="gad4008be388657e20fcb49511a5d38a3e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_ERR_RLENER_MASK&#160;&#160;&#160;0x00010000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen__hw_8h.html">xtrafgen_hw.h</a>&gt;</code></p>

<p>Master Read Length Mask. </p>

</div>
</div>
<a class="anchor" id="ga6d44ba5c998cf48c8162812f1b183cfa"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_ERR_STS_OFFSET&#160;&#160;&#160;0x08</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen__hw_8h.html">xtrafgen_hw.h</a>&gt;</code></p>

<p>Error Status. </p>

</div>
</div>
<a class="anchor" id="ga8f39b5d4a784a673cad5225ac1253f1b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_ERR_SWLENER_MASK&#160;&#160;&#160;0x00000001</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen__hw_8h.html">xtrafgen_hw.h</a>&gt;</code></p>

<p>Slave Read Length Mask. </p>

</div>
</div>
<a class="anchor" id="ga9585c4a750db5e61e49ada2c30d2cc71"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_ERR_SWSTRB_MASK&#160;&#160;&#160;0x00000002</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen__hw_8h.html">xtrafgen_hw.h</a>&gt;</code></p>

<p>Slave WSTRB Illegal Mask. </p>

</div>
</div>
<a class="anchor" id="ga93be7e7fdaaa372c2b888c07ecfd6466"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_ERR_WIDER_MASK&#160;&#160;&#160;0x00080000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen__hw_8h.html">xtrafgen_hw.h</a>&gt;</code></p>

<p>Master Invalid BVALID Mask. </p>

</div>
</div>
<a class="anchor" id="ga6e70386e2b3071efc1391dea0c6d7ff7"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_ERR_WRSPER_MASK&#160;&#160;&#160;0x00040000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen__hw_8h.html">xtrafgen_hw.h</a>&gt;</code></p>

<p>MW Invalid RESP Mask. </p>

</div>
</div>
<a class="anchor" id="gac0e4ea9cbcd6fb559351aee0f810d60b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_EXTCMD_RAM_BLOCK_SIZE&#160;&#160;&#160;0x400</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>

<p>Extended CMDRAM Block Size (1KB) </p>

</div>
</div>
<a class="anchor" id="ga5f8872e23f0ea33fda1193c114fa9224"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_MASTER_RAM_OFFSET&#160;&#160;&#160;0xC000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen__hw_8h.html">xtrafgen_hw.h</a>&gt;</code></p>

<p>Master RAM Offset. </p>

</div>
</div>
<a class="anchor" id="ga255c930454b0fb1a4a1b9dbe7c704692"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_MASTER_RAM_SIZE&#160;&#160;&#160;0x2000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>

<p>Master RAM (8KB) </p>

<p>Referenced by <a class="el" href="group__trafgen__v3__2.html#gaaea625b89454268bbbe7f93e309141c4">XTrafGen_AccessMasterRam()</a>.</p>

</div>
</div>
<a class="anchor" id="ga736a0c4efcd60c172f0c5b5bc19fa11b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_MCNTL_LOOPEN_MASK&#160;&#160;&#160;0x00080000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen__hw_8h.html">xtrafgen_hw.h</a>&gt;</code></p>

<p>Loop enable Mask. </p>

</div>
</div>
<a class="anchor" id="gaf8fafcd0c1061fbf9d6d61680a251309"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_MCNTL_MSTEN_MASK&#160;&#160;&#160;0x00100000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen__hw_8h.html">xtrafgen_hw.h</a>&gt;</code></p>

<p>Master Logic Enable Mask. </p>

</div>
</div>
<a class="anchor" id="ga912b534ed07c85f5147d86a5125e6cd8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_MCNTL_MSTID_MASK&#160;&#160;&#160;0x00E00000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen__hw_8h.html">xtrafgen_hw.h</a>&gt;</code></p>

<p>M_ID_WIDTH Mask. </p>

</div>
</div>
<a class="anchor" id="gab849a5c24ef2753d38f62531ed5dcba9"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_MCNTL_MSTID_SHIFT&#160;&#160;&#160;21</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen__hw_8h.html">xtrafgen_hw.h</a>&gt;</code></p>

<p>M_ID_WIDTH shift. </p>

</div>
</div>
<a class="anchor" id="ga2aee9e721b35ce512abb502ede5b8a06"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_MCNTL_OFFSET&#160;&#160;&#160;0x00</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen__hw_8h.html">xtrafgen_hw.h</a>&gt;</code></p>

<p>Master Control. </p>

</div>
</div>
<a class="anchor" id="ga2197ba1e4ea908189bc7d77e70ba5a06"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_MCNTL_REV_MASK&#160;&#160;&#160;0xFF000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen__hw_8h.html">xtrafgen_hw.h</a>&gt;</code></p>

<p>Core Revision Mask. </p>

</div>
</div>
<a class="anchor" id="ga07d0697117d702e5a767bc8cc5083ea0"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_MCNTL_REV_SHIFT&#160;&#160;&#160;24</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen__hw_8h.html">xtrafgen_hw.h</a>&gt;</code></p>

<p>Core Rev shift. </p>

</div>
</div>
<a class="anchor" id="ga4b6bd2e6c7f45de76c7fb1241c364347"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_MODE_BASIC&#160;&#160;&#160;1</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>

<p>Basic Mode. </p>

<p>Referenced by <a class="el" href="group__trafgen__v3__2.html#ga4d40f6d5551836dab49e0d22e8d5e1eb">XTrafGen_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="ga80fcb2c884f7369ddbaffc1e51bba9ce"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_MODE_FULL&#160;&#160;&#160;0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>

<p>Full Mode. </p>

<p>Referenced by <a class="el" href="group__trafgen__v3__2.html#ga4d40f6d5551836dab49e0d22e8d5e1eb">XTrafGen_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="ga15499801ae618925ac45a3a55807e1d6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_MODE_STATIC&#160;&#160;&#160;2</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>

<p>Static Mode. </p>

<p>Referenced by <a class="el" href="group__trafgen__v3__2.html#ga4d40f6d5551836dab49e0d22e8d5e1eb">XTrafGen_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="gaf22b2f8af4980fac9d5faaf3001ab0f0"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_MODE_STREAMING&#160;&#160;&#160;3</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>

<p>Streaming Mode. </p>

<p>Referenced by <a class="el" href="group__trafgen__v3__2.html#ga4d40f6d5551836dab49e0d22e8d5e1eb">XTrafGen_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="ga3d8b67e1ec714d525de17946ec19ad49"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_MODE_SYS_INIT&#160;&#160;&#160;4</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>

<p>System Init Mode. </p>

<p>Referenced by <a class="el" href="group__trafgen__v3__2.html#ga4d40f6d5551836dab49e0d22e8d5e1eb">XTrafGen_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="ga8549ea88039b3f646e33299b490b8904"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_MSTERR_INTR_OFFSET&#160;&#160;&#160;0x10</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen__hw_8h.html">xtrafgen_hw.h</a>&gt;</code></p>

<p>Master Err Interrupt Enable. </p>

</div>
</div>
<a class="anchor" id="ga7480264c1d222e138bcbc5174c388dfa"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_MWIDTH_32&#160;&#160;&#160;0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>

<p>Master Width - 32. </p>

</div>
</div>
<a class="anchor" id="ga3b8b2543e2717381d028703081f750d9"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_MWIDTH_64&#160;&#160;&#160;1</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>

<p>Master Width - 64. </p>

</div>
</div>
<a class="anchor" id="ga3252ba966b4231b39738858474879b33"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PARAM_RAM_OFFSET&#160;&#160;&#160;0x1000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen__hw_8h.html">xtrafgen_hw.h</a>&gt;</code></p>

<p>Parameter RAM Offset. </p>

</div>
</div>
<a class="anchor" id="ga97756bfb1f0735200a2668e7431ebcf3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PARAM_RAM_SIZE&#160;&#160;&#160;0x800</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>

<p>Parameter RAM (2KB) </p>

</div>
</div>
<a class="anchor" id="gaedc624adc68d449cdd422c2bcf824ae5"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PRM_RAM_BLOCK_SIZE&#160;&#160;&#160;0x400</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>

<p>PARAM Block Size (1KB) </p>

</div>
</div>
<a class="anchor" id="ga2391f0c6f6705906f85e0da3d16e3222"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_READ&#160;&#160;&#160;0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>

<p>Read Direction Flag. </p>

</div>
</div>
<a class="anchor" id="ga8a90a170c2c59e105bca09bf32cc5762"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_SCNTL_BLKRD_MASK&#160;&#160;&#160;0x00080000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen__hw_8h.html">xtrafgen_hw.h</a>&gt;</code></p>

<p>Enable Block Read. </p>

</div>
</div>
<a class="anchor" id="ga68091fdd6f9b82d0d6bf65c92b131e38"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_SCNTL_DISEXCL_MASK&#160;&#160;&#160;0x00040000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen__hw_8h.html">xtrafgen_hw.h</a>&gt;</code></p>

<p>Disable Exclusive Access. </p>

</div>
</div>
<a class="anchor" id="gab3fd9e680a247d1ad78ba6cab9b061fb"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_SCNTL_ERREN_MASK&#160;&#160;&#160;0x00008000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen__hw_8h.html">xtrafgen_hw.h</a>&gt;</code></p>

<p>Slv Error Interrupt Enable. </p>

</div>
</div>
<a class="anchor" id="ga16ab165b5d7fd7c84206606b1bc2dcfa"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_SCNTL_OFFSET&#160;&#160;&#160;0x04</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen__hw_8h.html">xtrafgen_hw.h</a>&gt;</code></p>

<p>Slave Control. </p>

</div>
</div>
<a class="anchor" id="gadd90aa32d6ffdb6c248aae48b4d03990"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_SCNTL_RORDR_MASK&#160;&#160;&#160;0x00010000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen__hw_8h.html">xtrafgen_hw.h</a>&gt;</code></p>

<p>Read Response Order Enable. </p>

</div>
</div>
<a class="anchor" id="ga05a3dd5b5ff4ddb1ed8bd33f091893d3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_SCNTL_WORDR_MASK&#160;&#160;&#160;0x00020000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen__hw_8h.html">xtrafgen_hw.h</a>&gt;</code></p>

<p>Write Response Order Enable. </p>

</div>
</div>
<a class="anchor" id="gafee2ca23e3fc2ed4964740ba69dde023"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_STATIC_CNTL_OFFSET&#160;&#160;&#160;0x60</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen__hw_8h.html">xtrafgen_hw.h</a>&gt;</code></p>

<p>Static Mode Register Descrptions. </p>
<p>Static Control </p>

</div>
</div>
<a class="anchor" id="ga1813133f0d9bd28861fac1a854137411"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_STATIC_LEN_OFFSET&#160;&#160;&#160;0x64</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen__hw_8h.html">xtrafgen_hw.h</a>&gt;</code></p>

<p>Static Length. </p>

</div>
</div>
<a class="anchor" id="ga0faa9082cff01c4e5e53bb957b69dae2"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_STREAM_CFG_OFFSET&#160;&#160;&#160;0x34</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen__hw_8h.html">xtrafgen_hw.h</a>&gt;</code></p>

<p>Streaming Config. </p>

</div>
</div>
<a class="anchor" id="gadad67dedb6f0b5c0e7aed2e0d62e08eb"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_STREAM_CNTL_OFFSET&#160;&#160;&#160;0x30</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen__hw_8h.html">xtrafgen_hw.h</a>&gt;</code></p>

<p>Streaming Control. </p>

</div>
</div>
<a class="anchor" id="ga476caa717b80c4d276d7ff98aae5f3ca"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_STREAM_TL_OFFSET&#160;&#160;&#160;0x38</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen__hw_8h.html">xtrafgen_hw.h</a>&gt;</code></p>

<p>Streaming Transfer Length. </p>

</div>
</div>
<a class="anchor" id="ga01688e8360ce4e2f5f0b3fbb005ca32f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_SWIDTH_32&#160;&#160;&#160;0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>

<p>Slave Width - 32. </p>

</div>
</div>
<a class="anchor" id="ga9a40084992daaaba41ea6f395153a417"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_SWIDTH_64&#160;&#160;&#160;1</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>

<p>Slave Width - 64. </p>

</div>
</div>
<a class="anchor" id="ga8a676092267b72a3e5ad91718b914ecf"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_WRITE&#160;&#160;&#160;1</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>

<p>Write Direction Flag. </p>

<p>Referenced by <a class="el" href="group__trafgen__v3__2.html#gaaea625b89454268bbbe7f93e309141c4">XTrafGen_AccessMasterRam()</a>, <a class="el" href="group__trafgen__v3__2.html#ga39eaea669c1ff2df58e54c002b43f854">XTrafGen_AddCommand()</a>, and <a class="el" href="group__trafgen__v3__2.html#ga262d850cbfc5b0495fbc2d84334a1fba">XTrafGen_GetLastValidIndex()</a>.</p>

</div>
</div>
<a class="anchor" id="ga1e86bf806f4ae36b671eef5f97b0b822"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTrafGen_CheckforMasterComplete</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">((<a class="code" href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress,   \</div>
<div class="line">                <a class="code" href="group__trafgen__v3__2.html#ga6d44ba5c998cf48c8162812f1b183cfa">XTG_ERR_STS_OFFSET</a>) &amp; <a class="code" href="group__trafgen__v3__2.html#ga5cefaef257524651df762212be509765">XTG_ERR_MSTCMP_MASK</a>) ? TRUE : FALSE)</div>
<div class="ttc" id="group__trafgen__v3__2_html_ga6d44ba5c998cf48c8162812f1b183cfa"><div class="ttname"><a href="group__trafgen__v3__2.html#ga6d44ba5c998cf48c8162812f1b183cfa">XTG_ERR_STS_OFFSET</a></div><div class="ttdeci">#define XTG_ERR_STS_OFFSET</div><div class="ttdoc">Error Status. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:88</div></div>
<div class="ttc" id="group__trafgen__v3__2_html_ga5cefaef257524651df762212be509765"><div class="ttname"><a href="group__trafgen__v3__2.html#ga5cefaef257524651df762212be509765">XTG_ERR_MSTCMP_MASK</a></div><div class="ttdeci">#define XTG_ERR_MSTCMP_MASK</div><div class="ttdoc">Master Complete Mask. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:167</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_affb7c95abd8cad50d7efa83f94ea3344"><div class="ttname"><a href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a></div><div class="ttdeci">#define XTrafGen_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...</div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:404</div></div>
</div><!-- fragment -->
<p>XTrafGen_CheckforMasterComplete checks for master complete. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Axi TrafGen instance to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>TRUE if master complete bit is set. FALSE if master complete bit is not set.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u8 <a class="el" href="group__trafgen__v3__2.html#ga1e86bf806f4ae36b671eef5f97b0b822" title="XTrafGen_CheckforMasterComplete checks for master complete. ">XTrafGen_CheckforMasterComplete(XTrafGen *InstancePtr)</a> </dd></dl>

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<a class="anchor" id="gae1c90008bc5f3e300bd90f5ce1496793"></a>
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          <td class="memname">#define XTrafGen_ClearErrors</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Mask&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xtrafgen__hw_8h.html#ac6e57b26c1f5674deb7c571dc319bf9e">XTrafGen_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress,    \</div>
<div class="line">                <a class="code" href="group__trafgen__v3__2.html#ga6d44ba5c998cf48c8162812f1b183cfa">XTG_ERR_STS_OFFSET</a>,     \</div>
<div class="line">                (<a class="code" href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress,    \</div>
<div class="line">                        <a class="code" href="group__trafgen__v3__2.html#ga6d44ba5c998cf48c8162812f1b183cfa">XTG_ERR_STS_OFFSET</a>) | Mask))</div>
<div class="ttc" id="xtrafgen__hw_8h_html_ac6e57b26c1f5674deb7c571dc319bf9e"><div class="ttname"><a href="xtrafgen__hw_8h.html#ac6e57b26c1f5674deb7c571dc319bf9e">XTrafGen_WriteReg</a></div><div class="ttdeci">#define XTrafGen_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">XTrafGen_WriteReg, writes Data to the register specified by RegOffset. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:424</div></div>
<div class="ttc" id="group__trafgen__v3__2_html_ga6d44ba5c998cf48c8162812f1b183cfa"><div class="ttname"><a href="group__trafgen__v3__2.html#ga6d44ba5c998cf48c8162812f1b183cfa">XTG_ERR_STS_OFFSET</a></div><div class="ttdeci">#define XTG_ERR_STS_OFFSET</div><div class="ttdoc">Error Status. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:88</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_affb7c95abd8cad50d7efa83f94ea3344"><div class="ttname"><a href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a></div><div class="ttdeci">#define XTrafGen_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...</div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:404</div></div>
</div><!-- fragment -->
<p>XTrafGen_ClearErrors clear errors specified in <em>Mask</em>. </p>
<p>The corresponding error for each bit set to 1 in <em>Mask</em>, will be enabled.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Axi TrafGen instance to be worked on. </td></tr>
    <tr><td class="paramname">Mask</td><td>contains a bit mask of the errors to clear. The mask can be formed using a set of bit wise or'd values from the definitions in <a class="el" href="xtrafgen__hw_8h.html">xtrafgen_hw.h</a> file.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void XTrafGen_ClearErrors(<a class="el" href="struct_x_traf_gen.html" title="The XTrafGen driver instance data. ">XTrafGen</a> *InstancePtr, u32 Mask) </dd></dl>

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<a class="anchor" id="gadb9dd3596754f92d6c3dc73c957e812f"></a>
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        <tr>
          <td class="memname">#define XTrafGen_ClearMasterCmpInterrupt</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xtrafgen__hw_8h.html#ac6e57b26c1f5674deb7c571dc319bf9e">XTrafGen_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress,    \</div>
<div class="line">                <a class="code" href="group__trafgen__v3__2.html#ga6d44ba5c998cf48c8162812f1b183cfa">XTG_ERR_STS_OFFSET</a>,     \</div>
<div class="line">                (<a class="code" href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress,    \</div>
<div class="line">                        <a class="code" href="group__trafgen__v3__2.html#ga6d44ba5c998cf48c8162812f1b183cfa">XTG_ERR_STS_OFFSET</a>) |   \</div>
<div class="line">                        <a class="code" href="group__trafgen__v3__2.html#ga5cefaef257524651df762212be509765">XTG_ERR_MSTCMP_MASK</a>))</div>
<div class="ttc" id="xtrafgen__hw_8h_html_ac6e57b26c1f5674deb7c571dc319bf9e"><div class="ttname"><a href="xtrafgen__hw_8h.html#ac6e57b26c1f5674deb7c571dc319bf9e">XTrafGen_WriteReg</a></div><div class="ttdeci">#define XTrafGen_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">XTrafGen_WriteReg, writes Data to the register specified by RegOffset. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:424</div></div>
<div class="ttc" id="group__trafgen__v3__2_html_ga6d44ba5c998cf48c8162812f1b183cfa"><div class="ttname"><a href="group__trafgen__v3__2.html#ga6d44ba5c998cf48c8162812f1b183cfa">XTG_ERR_STS_OFFSET</a></div><div class="ttdeci">#define XTG_ERR_STS_OFFSET</div><div class="ttdoc">Error Status. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:88</div></div>
<div class="ttc" id="group__trafgen__v3__2_html_ga5cefaef257524651df762212be509765"><div class="ttname"><a href="group__trafgen__v3__2.html#ga5cefaef257524651df762212be509765">XTG_ERR_MSTCMP_MASK</a></div><div class="ttdeci">#define XTG_ERR_MSTCMP_MASK</div><div class="ttdoc">Master Complete Mask. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:167</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_affb7c95abd8cad50d7efa83f94ea3344"><div class="ttname"><a href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a></div><div class="ttdeci">#define XTrafGen_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...</div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:404</div></div>
</div><!-- fragment -->
<p>XTrafGen_ClearMasterCmpInterrupt clear Master logic complete interrupt bit. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Axi TrafGen instance to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u8 <a class="el" href="group__trafgen__v3__2.html#gadb9dd3596754f92d6c3dc73c957e812f" title="XTrafGen_ClearMasterCmpInterrupt clear Master logic complete interrupt bit. ">XTrafGen_ClearMasterCmpInterrupt(XTrafGen *InstancePtr)</a> </dd></dl>

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<a class="anchor" id="ga6e6159d969c5f451f429b9d8ec4a42f8"></a>
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        <tr>
          <td class="memname">#define XTrafGen_EnableErrors</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Mask&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xtrafgen__hw_8h.html#ac6e57b26c1f5674deb7c571dc319bf9e">XTrafGen_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress,    \</div>
<div class="line">                <a class="code" href="group__trafgen__v3__2.html#ga54f00a5d7ea7acb0a8917b79f6aeeb57">XTG_ERR_EN_OFFSET</a>,      \</div>
<div class="line">                (<a class="code" href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress,    \</div>
<div class="line">                        <a class="code" href="group__trafgen__v3__2.html#ga54f00a5d7ea7acb0a8917b79f6aeeb57">XTG_ERR_EN_OFFSET</a>) | Mask))</div>
<div class="ttc" id="xtrafgen__hw_8h_html_ac6e57b26c1f5674deb7c571dc319bf9e"><div class="ttname"><a href="xtrafgen__hw_8h.html#ac6e57b26c1f5674deb7c571dc319bf9e">XTrafGen_WriteReg</a></div><div class="ttdeci">#define XTrafGen_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">XTrafGen_WriteReg, writes Data to the register specified by RegOffset. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:424</div></div>
<div class="ttc" id="group__trafgen__v3__2_html_ga54f00a5d7ea7acb0a8917b79f6aeeb57"><div class="ttname"><a href="group__trafgen__v3__2.html#ga54f00a5d7ea7acb0a8917b79f6aeeb57">XTG_ERR_EN_OFFSET</a></div><div class="ttdeci">#define XTG_ERR_EN_OFFSET</div><div class="ttdoc">Error Enable. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:89</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_affb7c95abd8cad50d7efa83f94ea3344"><div class="ttname"><a href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a></div><div class="ttdeci">#define XTrafGen_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...</div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:404</div></div>
</div><!-- fragment -->
<p>XTrafGen_EnableErrors enable errors specified in <em>Mask</em>. </p>
<p>The corresponding error for each bit set to 1 in <em>Mask</em>, will be enabled.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Axi TrafGen instance to be worked on. </td></tr>
    <tr><td class="paramname">Mask</td><td>contains a bit mask of the errors to enable. The mask can be formed using a set of bit wise or'd values from the definitions in <a class="el" href="xtrafgen__hw_8h.html">xtrafgen_hw.h</a> file.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void XTrafGen_EnableErrors(<a class="el" href="struct_x_traf_gen.html" title="The XTrafGen driver instance data. ">XTrafGen</a> *InstancePtr, u32 Mask) </dd></dl>

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<a class="anchor" id="ga11a588bff0d2c58310d48da4c24126a1"></a>
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          <td class="memname">#define XTrafGen_EnableMasterCmpInterrupt</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xtrafgen__hw_8h.html#ac6e57b26c1f5674deb7c571dc319bf9e">XTrafGen_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress,    \</div>
<div class="line">                <a class="code" href="group__trafgen__v3__2.html#ga54f00a5d7ea7acb0a8917b79f6aeeb57">XTG_ERR_EN_OFFSET</a>,      \</div>
<div class="line">                (<a class="code" href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress,    \</div>
<div class="line">                        <a class="code" href="group__trafgen__v3__2.html#ga54f00a5d7ea7acb0a8917b79f6aeeb57">XTG_ERR_EN_OFFSET</a>) |    \</div>
<div class="line">                        <a class="code" href="group__trafgen__v3__2.html#ga5cefaef257524651df762212be509765">XTG_ERR_MSTCMP_MASK</a>))</div>
<div class="ttc" id="xtrafgen__hw_8h_html_ac6e57b26c1f5674deb7c571dc319bf9e"><div class="ttname"><a href="xtrafgen__hw_8h.html#ac6e57b26c1f5674deb7c571dc319bf9e">XTrafGen_WriteReg</a></div><div class="ttdeci">#define XTrafGen_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">XTrafGen_WriteReg, writes Data to the register specified by RegOffset. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:424</div></div>
<div class="ttc" id="group__trafgen__v3__2_html_ga54f00a5d7ea7acb0a8917b79f6aeeb57"><div class="ttname"><a href="group__trafgen__v3__2.html#ga54f00a5d7ea7acb0a8917b79f6aeeb57">XTG_ERR_EN_OFFSET</a></div><div class="ttdeci">#define XTG_ERR_EN_OFFSET</div><div class="ttdoc">Error Enable. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:89</div></div>
<div class="ttc" id="group__trafgen__v3__2_html_ga5cefaef257524651df762212be509765"><div class="ttname"><a href="group__trafgen__v3__2.html#ga5cefaef257524651df762212be509765">XTG_ERR_MSTCMP_MASK</a></div><div class="ttdeci">#define XTG_ERR_MSTCMP_MASK</div><div class="ttdoc">Master Complete Mask. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:167</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_affb7c95abd8cad50d7efa83f94ea3344"><div class="ttname"><a href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a></div><div class="ttdeci">#define XTrafGen_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...</div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:404</div></div>
</div><!-- fragment -->
<p>XTrafGen_EnableMasterCmpInterrupt enables Master logic complete bit. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Axi TrafGen instance to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__trafgen__v3__2.html#ga11a588bff0d2c58310d48da4c24126a1" title="XTrafGen_EnableMasterCmpInterrupt enables Master logic complete bit. ">XTrafGen_EnableMasterCmpInterrupt(XTrafGen *InstancePtr)</a> </dd></dl>

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          <td class="memname">#define XTrafGen_GetCmdInfo</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td>&#160;&#160;&#160;(&amp;((InstancePtr)-&gt;CmdInfo))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8c.html">xtrafgen.c</a>&gt;</code></p>

<p>Get Command Info pointer. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Axi TrafGen instance to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Pointer to the Command Info structure</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: <a class="el" href="struct_x_traf_gen___cmd_info.html" title="Command Information Structure. ">XTrafGen_CmdInfo</a> *XTrafGen_GetCmdInfo(<a class="el" href="struct_x_traf_gen.html" title="The XTrafGen driver instance data. ">XTrafGen</a> *InstancePtr) </dd></dl>

<p>Referenced by <a class="el" href="group__trafgen__v3__2.html#ga39eaea669c1ff2df58e54c002b43f854">XTrafGen_AddCommand()</a>, <a class="el" href="group__trafgen__v3__2.html#ga539d4976ad3ace9e15d993e2b18143a0">XTrafGen_EraseAllCommands()</a>, <a class="el" href="group__trafgen__v3__2.html#ga262d850cbfc5b0495fbc2d84334a1fba">XTrafGen_GetLastValidIndex()</a>, and <a class="el" href="group__trafgen__v3__2.html#gad9654a81e902175a963c83edb0c37144">XTrafGen_PrintCmds()</a>.</p>

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          <td class="memname">#define XTrafGen_GetStaticBurstLen</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress,    \</div>
<div class="line">                <a class="code" href="group__trafgen__v3__2.html#ga1813133f0d9bd28861fac1a854137411">XTG_STATIC_LEN_OFFSET</a>))</div>
<div class="ttc" id="group__trafgen__v3__2_html_ga1813133f0d9bd28861fac1a854137411"><div class="ttname"><a href="group__trafgen__v3__2.html#ga1813133f0d9bd28861fac1a854137411">XTG_STATIC_LEN_OFFSET</a></div><div class="ttdeci">#define XTG_STATIC_LEN_OFFSET</div><div class="ttdoc">Static Length. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:100</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_affb7c95abd8cad50d7efa83f94ea3344"><div class="ttname"><a href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a></div><div class="ttdeci">#define XTrafGen_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...</div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:404</div></div>
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<p>XTrafGen_GetStaticBurstLen Gets the Burst Length for AxiTrafGen in StaticMode. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Axi TrafGen instance to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Burst length value.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__trafgen__v3__2.html#gaedebd87b7d6727d97552da64fbb16d69" title="XTrafGen_GetStaticBurstLen Gets the Burst Length for AxiTrafGen in StaticMode. ">XTrafGen_GetStaticBurstLen(XTrafGen *InstancePtr)</a> </dd></dl>

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          <td class="memname">#define XTrafGen_GetStaticTransferDone</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">((<a class="code" href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress,   \</div>
<div class="line">                        <a class="code" href="group__trafgen__v3__2.html#gafee2ca23e3fc2ed4964740ba69dde023">XTG_STATIC_CNTL_OFFSET</a>)) &amp; <a class="code" href="xtrafgen__hw_8h.html#ae82296e2d81edb5da14c813e36b604cc">XTG_STATIC_CNTL_TD_MASK</a>)</div>
<div class="ttc" id="group__trafgen__v3__2_html_gafee2ca23e3fc2ed4964740ba69dde023"><div class="ttname"><a href="group__trafgen__v3__2.html#gafee2ca23e3fc2ed4964740ba69dde023">XTG_STATIC_CNTL_OFFSET</a></div><div class="ttdeci">#define XTG_STATIC_CNTL_OFFSET</div><div class="ttdoc">Static Mode Register Descrptions. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:99</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_ae82296e2d81edb5da14c813e36b604cc"><div class="ttname"><a href="xtrafgen__hw_8h.html#ae82296e2d81edb5da14c813e36b604cc">XTG_STATIC_CNTL_TD_MASK</a></div><div class="ttdeci">#define XTG_STATIC_CNTL_TD_MASK</div><div class="ttdoc">Transfer Done Mask. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:288</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_affb7c95abd8cad50d7efa83f94ea3344"><div class="ttname"><a href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a></div><div class="ttdeci">#define XTrafGen_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...</div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:404</div></div>
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<p>XTrafGen_GetStaticTransferDone gets the state of Transfer done bit in Control register When the TraficGen is configured in Static Mode. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Axi TrafGen instance to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Value of the Tranfer Done bit.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__trafgen__v3__2.html#ga7b1b98f0a7cb8a9dca62ecadbc1d6d42" title="XTrafGen_GetStaticTransferDone gets the state of Transfer done bit in Control register When the Trafi...">XTrafGen_GetStaticTransferDone(XTrafGen *InstancePtr)</a> </dd></dl>

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          <td class="memname">#define XTrafGen_GetStreamingProgDelay</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">((<a class="code" href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                <a class="code" href="group__trafgen__v3__2.html#ga476caa717b80c4d276d7ff98aae5f3ca">XTG_STREAM_TL_OFFSET</a> ) \</div>
<div class="line">                &amp; <a class="code" href="xtrafgen__hw_8h.html#a490ccc5cf897e6daf0e403fdb5028cc8">XTG_STREAM_CFG_PDLY_MASK</a>) &gt;&gt; <a class="code" href="xtrafgen__hw_8h.html#aea7d215adbbf69b18fac485e2d150bd9">XTG_STREAM_CFG_PDLY_SHIFT</a>)</div>
<div class="ttc" id="xtrafgen__hw_8h_html_aea7d215adbbf69b18fac485e2d150bd9"><div class="ttname"><a href="xtrafgen__hw_8h.html#aea7d215adbbf69b18fac485e2d150bd9">XTG_STREAM_CFG_PDLY_SHIFT</a></div><div class="ttdeci">#define XTG_STREAM_CFG_PDLY_SHIFT</div><div class="ttdoc">Programmable Delay Shift. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:255</div></div>
<div class="ttc" id="group__trafgen__v3__2_html_ga476caa717b80c4d276d7ff98aae5f3ca"><div class="ttname"><a href="group__trafgen__v3__2.html#ga476caa717b80c4d276d7ff98aae5f3ca">XTG_STREAM_TL_OFFSET</a></div><div class="ttdeci">#define XTG_STREAM_TL_OFFSET</div><div class="ttdoc">Streaming Transfer Length. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:94</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_a490ccc5cf897e6daf0e403fdb5028cc8"><div class="ttname"><a href="xtrafgen__hw_8h.html#a490ccc5cf897e6daf0e403fdb5028cc8">XTG_STREAM_CFG_PDLY_MASK</a></div><div class="ttdeci">#define XTG_STREAM_CFG_PDLY_MASK</div><div class="ttdoc">Programmable Delay Mask. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:256</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_affb7c95abd8cad50d7efa83f94ea3344"><div class="ttname"><a href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a></div><div class="ttdeci">#define XTrafGen_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...</div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:404</div></div>
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<p>XTrafGen_GetStreamingProgDelay Gets the Programmable Delay for AxiTrafGen in Streaming Mode. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Axi TrafGen instance to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Propagation Delay Value</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u16 XTrafGen_GetProgDelay(XTrafGen *InstancePtr) </dd></dl>

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          <td class="memname">#define XTrafGen_GetStreamingTransCnt</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">((<a class="code" href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                <a class="code" href="group__trafgen__v3__2.html#ga476caa717b80c4d276d7ff98aae5f3ca">XTG_STREAM_TL_OFFSET</a> ) &amp; <a class="code" href="xtrafgen__hw_8h.html#a556bcb7b08d4170167ee65c08c7a0ebe">XTG_STREAM_TL_TCNT_MASK</a>) \</div>
<div class="line">                &gt;&gt; <a class="code" href="xtrafgen__hw_8h.html#a826017ee56ef1171a4d132dc12ca8341">XTG_STREAM_TL_TCNT_SHIFT</a>)</div>
<div class="ttc" id="group__trafgen__v3__2_html_ga476caa717b80c4d276d7ff98aae5f3ca"><div class="ttname"><a href="group__trafgen__v3__2.html#ga476caa717b80c4d276d7ff98aae5f3ca">XTG_STREAM_TL_OFFSET</a></div><div class="ttdeci">#define XTG_STREAM_TL_OFFSET</div><div class="ttdoc">Streaming Transfer Length. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:94</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_a826017ee56ef1171a4d132dc12ca8341"><div class="ttname"><a href="xtrafgen__hw_8h.html#a826017ee56ef1171a4d132dc12ca8341">XTG_STREAM_TL_TCNT_SHIFT</a></div><div class="ttdeci">#define XTG_STREAM_TL_TCNT_SHIFT</div><div class="ttdoc">Transfer Count Shift. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:273</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_a556bcb7b08d4170167ee65c08c7a0ebe"><div class="ttname"><a href="xtrafgen__hw_8h.html#a556bcb7b08d4170167ee65c08c7a0ebe">XTG_STREAM_TL_TCNT_MASK</a></div><div class="ttdeci">#define XTG_STREAM_TL_TCNT_MASK</div><div class="ttdoc">Transfer Count Mask. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:274</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_affb7c95abd8cad50d7efa83f94ea3344"><div class="ttname"><a href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a></div><div class="ttdeci">#define XTrafGen_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...</div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:404</div></div>
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<p>XTrafGen_GetStreamingTransCnt Gets the transfer count for AxiTrafGen in Streaming Mode. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Axi TrafGen instance to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Transfer Count value.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u16 <a class="el" href="group__trafgen__v3__2.html#ga9628f47e6f85fc3dba9f55c4b28b2e69" title="XTrafGen_GetStreamingTransCnt Gets the transfer count for AxiTrafGen in Streaming Mode...">XTrafGen_GetStreamingTransCnt(XTrafGen *InstancePtr)</a> </dd></dl>

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<a class="anchor" id="gaf17c0eadf5962f5dd8ba970b77dd12e6"></a>
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          <td class="memname">#define XTrafGen_GetStreamingTransLen</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a>(InstancePtr-&gt;Config.BaseAddress,      \</div>
<div class="line">                <a class="code" href="group__trafgen__v3__2.html#ga476caa717b80c4d276d7ff98aae5f3ca">XTG_STREAM_TL_OFFSET</a>)&amp; <a class="code" href="xtrafgen__hw_8h.html#ae28f53acd7ef1f38265f560c17c64800">XTG_STREAM_TL_TLEN_MASK</a>)</div>
<div class="ttc" id="xtrafgen__hw_8h_html_ae28f53acd7ef1f38265f560c17c64800"><div class="ttname"><a href="xtrafgen__hw_8h.html#ae28f53acd7ef1f38265f560c17c64800">XTG_STREAM_TL_TLEN_MASK</a></div><div class="ttdeci">#define XTG_STREAM_TL_TLEN_MASK</div><div class="ttdoc">Transfer Length Mask. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:276</div></div>
<div class="ttc" id="group__trafgen__v3__2_html_ga476caa717b80c4d276d7ff98aae5f3ca"><div class="ttname"><a href="group__trafgen__v3__2.html#ga476caa717b80c4d276d7ff98aae5f3ca">XTG_STREAM_TL_OFFSET</a></div><div class="ttdeci">#define XTG_STREAM_TL_OFFSET</div><div class="ttdoc">Streaming Transfer Length. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:94</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_affb7c95abd8cad50d7efa83f94ea3344"><div class="ttname"><a href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a></div><div class="ttdeci">#define XTrafGen_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...</div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:404</div></div>
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<p>XTrafGen_GetStreamingTransLen Gets the length of transaction for AxiTrafGen in Streaming Mode. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Axi TrafGen instance to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Transfer Length value.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u16 <a class="el" href="group__trafgen__v3__2.html#gaf17c0eadf5962f5dd8ba970b77dd12e6" title="XTrafGen_GetStreamingTransLen Gets the length of transaction for AxiTrafGen in Streaming Mode...">XTrafGen_GetStreamingTransLen(XTrafGen *InstancePtr)</a> </dd></dl>

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          <td class="memname">#define XTrafGen_IsMasterLogicDone</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">((<a class="code" href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress,   \</div>
<div class="line">                <a class="code" href="group__trafgen__v3__2.html#ga2aee9e721b35ce512abb502ede5b8a06">XTG_MCNTL_OFFSET</a>) &amp; <a class="code" href="group__trafgen__v3__2.html#gaf8fafcd0c1061fbf9d6d61680a251309">XTG_MCNTL_MSTEN_MASK</a>) ? \</div>
<div class="line">                FALSE : TRUE)</div>
<div class="ttc" id="group__trafgen__v3__2_html_gaf8fafcd0c1061fbf9d6d61680a251309"><div class="ttname"><a href="group__trafgen__v3__2.html#gaf8fafcd0c1061fbf9d6d61680a251309">XTG_MCNTL_MSTEN_MASK</a></div><div class="ttdeci">#define XTG_MCNTL_MSTEN_MASK</div><div class="ttdoc">Master Logic Enable Mask. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:120</div></div>
<div class="ttc" id="group__trafgen__v3__2_html_ga2aee9e721b35ce512abb502ede5b8a06"><div class="ttname"><a href="group__trafgen__v3__2.html#ga2aee9e721b35ce512abb502ede5b8a06">XTG_MCNTL_OFFSET</a></div><div class="ttdeci">#define XTG_MCNTL_OFFSET</div><div class="ttdoc">Master Control. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:86</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_affb7c95abd8cad50d7efa83f94ea3344"><div class="ttname"><a href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a></div><div class="ttdeci">#define XTrafGen_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...</div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:404</div></div>
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<p>XTrafGen_IsMasterLogicDone checks for traffic generator master logic completed bit. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Axi TrafGen instance to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>TRUE if master logic completed. FALSE if master logic not completed.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u8 <a class="el" href="group__trafgen__v3__2.html#ga067b6b58a33f91e8fb345224a12fd713" title="XTrafGen_IsMasterLogicDone checks for traffic generator master logic completed bit. ">XTrafGen_IsMasterLogicDone(XTrafGen *InstancePtr)</a> </dd></dl>

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<a class="anchor" id="ga865f2e2498c2c50c43b5f9c1abfc54e2"></a>
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        <tr>
          <td class="memname">#define XTrafGen_IsStaticTransferDone</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">(((<a class="code" href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress,  \</div>
<div class="line">                <a class="code" href="group__trafgen__v3__2.html#gafee2ca23e3fc2ed4964740ba69dde023">XTG_STATIC_CNTL_OFFSET</a>) &amp; <a class="code" href="xtrafgen__hw_8h.html#ae82296e2d81edb5da14c813e36b604cc">XTG_STATIC_CNTL_TD_MASK</a>) == \</div>
<div class="line">                <a class="code" href="xtrafgen__hw_8h.html#a4955ccf9832cc09dd5f05b54f49104dd">XTG_STATIC_CNTL_RESET_MASK</a>) ? \</div>
<div class="line">                TRUE : FALSE)</div>
<div class="ttc" id="xtrafgen__hw_8h_html_a4955ccf9832cc09dd5f05b54f49104dd"><div class="ttname"><a href="xtrafgen__hw_8h.html#a4955ccf9832cc09dd5f05b54f49104dd">XTG_STATIC_CNTL_RESET_MASK</a></div><div class="ttdeci">#define XTG_STATIC_CNTL_RESET_MASK</div><div class="ttdoc">Static Disable Mask. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:291</div></div>
<div class="ttc" id="group__trafgen__v3__2_html_gafee2ca23e3fc2ed4964740ba69dde023"><div class="ttname"><a href="group__trafgen__v3__2.html#gafee2ca23e3fc2ed4964740ba69dde023">XTG_STATIC_CNTL_OFFSET</a></div><div class="ttdeci">#define XTG_STATIC_CNTL_OFFSET</div><div class="ttdoc">Static Mode Register Descrptions. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:99</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_ae82296e2d81edb5da14c813e36b604cc"><div class="ttname"><a href="xtrafgen__hw_8h.html#ae82296e2d81edb5da14c813e36b604cc">XTG_STATIC_CNTL_TD_MASK</a></div><div class="ttdeci">#define XTG_STATIC_CNTL_TD_MASK</div><div class="ttdoc">Transfer Done Mask. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:288</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_affb7c95abd8cad50d7efa83f94ea3344"><div class="ttname"><a href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a></div><div class="ttdeci">#define XTrafGen_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...</div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:404</div></div>
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<p>XTrafGen_IsStaticTransferDone checks for reset value When Static Traffic genration Completed by reading Control Register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Axi TrafGen instance to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>TRUE if reset Success full FALSE if failed to reset</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u8 <a class="el" href="group__trafgen__v3__2.html#ga865f2e2498c2c50c43b5f9c1abfc54e2" title="XTrafGen_IsStaticTransferDone checks for reset value When Static Traffic genration Completed by readi...">XTrafGen_IsStaticTransferDone(XTrafGen *InstancePtr)</a> </dd></dl>

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<a class="anchor" id="ga0ff0fea3c2324dbd0c6edc5efd5ba709"></a>
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          <td class="memname">#define XTrafGen_IsStreamingTransferDone</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">(((<a class="code" href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress,  \</div>
<div class="line">                <a class="code" href="group__trafgen__v3__2.html#gadad67dedb6f0b5c0e7aed2e0d62e08eb">XTG_STREAM_CNTL_OFFSET</a>) &amp; <a class="code" href="xtrafgen__hw_8h.html#a4b0674a7c9f7879bf6462860641b4d89">XTG_STREAM_CNTL_TD_MASK</a>) == \</div>
<div class="line">                <a class="code" href="xtrafgen__hw_8h.html#ad4ac7a7ef3c84748869c001e04d5dade">XTG_STREAM_CNTL_RESET_MASK</a>) ? \</div>
<div class="line">                TRUE : FALSE)</div>
<div class="ttc" id="xtrafgen__hw_8h_html_ad4ac7a7ef3c84748869c001e04d5dade"><div class="ttname"><a href="xtrafgen__hw_8h.html#ad4ac7a7ef3c84748869c001e04d5dade">XTG_STREAM_CNTL_RESET_MASK</a></div><div class="ttdeci">#define XTG_STREAM_CNTL_RESET_MASK</div><div class="ttdoc">Streaming Disable Mask. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:247</div></div>
<div class="ttc" id="group__trafgen__v3__2_html_gadad67dedb6f0b5c0e7aed2e0d62e08eb"><div class="ttname"><a href="group__trafgen__v3__2.html#gadad67dedb6f0b5c0e7aed2e0d62e08eb">XTG_STREAM_CNTL_OFFSET</a></div><div class="ttdeci">#define XTG_STREAM_CNTL_OFFSET</div><div class="ttdoc">Streaming Control. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:92</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_a4b0674a7c9f7879bf6462860641b4d89"><div class="ttname"><a href="xtrafgen__hw_8h.html#a4b0674a7c9f7879bf6462860641b4d89">XTG_STREAM_CNTL_TD_MASK</a></div><div class="ttdeci">#define XTG_STREAM_CNTL_TD_MASK</div><div class="ttdoc">Transfer Done Mask. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:244</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_affb7c95abd8cad50d7efa83f94ea3344"><div class="ttname"><a href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a></div><div class="ttdeci">#define XTrafGen_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...</div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:404</div></div>
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<p>XTrafGen_IsStreamingTransferDone checks for reset value When Streaming Traffic genration is Completed by reading Stream Control Register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Axi TrafGen instance to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>TRUE if reset Success full FALSE if failed to reset</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u8 <a class="el" href="group__trafgen__v3__2.html#ga0ff0fea3c2324dbd0c6edc5efd5ba709" title="XTrafGen_IsStreamingTransferDone checks for reset value When Streaming Traffic genration is Completed...">XTrafGen_IsStreamingTransferDone(XTrafGen *InstancePtr)</a> </dd></dl>

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        <tr>
          <td class="memname">#define XTrafGen_LoopDisable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xtrafgen__hw_8h.html#ac6e57b26c1f5674deb7c571dc319bf9e">XTrafGen_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress,    \</div>
<div class="line">                <a class="code" href="group__trafgen__v3__2.html#ga2aee9e721b35ce512abb502ede5b8a06">XTG_MCNTL_OFFSET</a>,       \</div>
<div class="line">                (<a class="code" href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress,    \</div>
<div class="line">                        <a class="code" href="group__trafgen__v3__2.html#ga2aee9e721b35ce512abb502ede5b8a06">XTG_MCNTL_OFFSET</a>) &amp; ~<a class="code" href="group__trafgen__v3__2.html#ga736a0c4efcd60c172f0c5b5bc19fa11b">XTG_MCNTL_LOOPEN_MASK</a>))</div>
<div class="ttc" id="xtrafgen__hw_8h_html_ac6e57b26c1f5674deb7c571dc319bf9e"><div class="ttname"><a href="xtrafgen__hw_8h.html#ac6e57b26c1f5674deb7c571dc319bf9e">XTrafGen_WriteReg</a></div><div class="ttdeci">#define XTrafGen_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">XTrafGen_WriteReg, writes Data to the register specified by RegOffset. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:424</div></div>
<div class="ttc" id="group__trafgen__v3__2_html_ga736a0c4efcd60c172f0c5b5bc19fa11b"><div class="ttname"><a href="group__trafgen__v3__2.html#ga736a0c4efcd60c172f0c5b5bc19fa11b">XTG_MCNTL_LOOPEN_MASK</a></div><div class="ttdeci">#define XTG_MCNTL_LOOPEN_MASK</div><div class="ttdoc">Loop enable Mask. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:123</div></div>
<div class="ttc" id="group__trafgen__v3__2_html_ga2aee9e721b35ce512abb502ede5b8a06"><div class="ttname"><a href="group__trafgen__v3__2.html#ga2aee9e721b35ce512abb502ede5b8a06">XTG_MCNTL_OFFSET</a></div><div class="ttdeci">#define XTG_MCNTL_OFFSET</div><div class="ttdoc">Master Control. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:86</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_affb7c95abd8cad50d7efa83f94ea3344"><div class="ttname"><a href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a></div><div class="ttdeci">#define XTrafGen_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...</div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:404</div></div>
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<p>XTrafGen_LoopDisable Disbales the loop bit in Master control regiset in Advanced mode/Basic mode of ATG. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Axi TrafGen instance to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__trafgen__v3__2.html#gad1d6d337106b8d03118d625159a93cf4" title="XTrafGen_LoopDisable Disbales the loop bit in Master control regiset in Advanced mode/Basic mode of A...">XTrafGen_LoopDisable(XTrafGen *InstancePtr)</a> </dd></dl>

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        <tr>
          <td class="memname">#define XTrafGen_LoopEnable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xtrafgen__hw_8h.html#ac6e57b26c1f5674deb7c571dc319bf9e">XTrafGen_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress,    \</div>
<div class="line">                <a class="code" href="group__trafgen__v3__2.html#ga2aee9e721b35ce512abb502ede5b8a06">XTG_MCNTL_OFFSET</a>,       \</div>
<div class="line">                (<a class="code" href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress,    \</div>
<div class="line">                        <a class="code" href="group__trafgen__v3__2.html#ga2aee9e721b35ce512abb502ede5b8a06">XTG_MCNTL_OFFSET</a>) | <a class="code" href="group__trafgen__v3__2.html#ga736a0c4efcd60c172f0c5b5bc19fa11b">XTG_MCNTL_LOOPEN_MASK</a>))</div>
<div class="ttc" id="xtrafgen__hw_8h_html_ac6e57b26c1f5674deb7c571dc319bf9e"><div class="ttname"><a href="xtrafgen__hw_8h.html#ac6e57b26c1f5674deb7c571dc319bf9e">XTrafGen_WriteReg</a></div><div class="ttdeci">#define XTrafGen_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">XTrafGen_WriteReg, writes Data to the register specified by RegOffset. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:424</div></div>
<div class="ttc" id="group__trafgen__v3__2_html_ga736a0c4efcd60c172f0c5b5bc19fa11b"><div class="ttname"><a href="group__trafgen__v3__2.html#ga736a0c4efcd60c172f0c5b5bc19fa11b">XTG_MCNTL_LOOPEN_MASK</a></div><div class="ttdeci">#define XTG_MCNTL_LOOPEN_MASK</div><div class="ttdoc">Loop enable Mask. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:123</div></div>
<div class="ttc" id="group__trafgen__v3__2_html_ga2aee9e721b35ce512abb502ede5b8a06"><div class="ttname"><a href="group__trafgen__v3__2.html#ga2aee9e721b35ce512abb502ede5b8a06">XTG_MCNTL_OFFSET</a></div><div class="ttdeci">#define XTG_MCNTL_OFFSET</div><div class="ttdoc">Master Control. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:86</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_affb7c95abd8cad50d7efa83f94ea3344"><div class="ttname"><a href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a></div><div class="ttdeci">#define XTrafGen_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...</div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:404</div></div>
</div><!-- fragment -->
<p>XTrafGen_LoopEnable loops through the command set created using CMDRAM and PARAMRAM indefinitely in Advanced mode/Basic mode of ATG. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Axi TrafGen instance to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__trafgen__v3__2.html#ga7ae20ec6a0531e09e0723905c20bb572" title="XTrafGen_LoopEnable loops through the command set created using CMDRAM and PARAMRAM indefinitely in A...">XTrafGen_LoopEnable(XTrafGen *InstancePtr)</a> </dd></dl>

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          <td class="memname">#define XTrafGen_MasterErrIntrDisable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xtrafgen__hw_8h.html#ac6e57b26c1f5674deb7c571dc319bf9e">XTrafGen_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress,  \</div>
<div class="line">                <a class="code" href="group__trafgen__v3__2.html#ga8549ea88039b3f646e33299b490b8904">XTG_MSTERR_INTR_OFFSET</a>, \</div>
<div class="line">                (<a class="code" href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                        <a class="code" href="group__trafgen__v3__2.html#ga8549ea88039b3f646e33299b490b8904">XTG_MSTERR_INTR_OFFSET</a>) &amp;       \</div>
<div class="line">                        ~<a class="code" href="xtrafgen__hw_8h.html#a7f69f7e850cdf6eaeacb76be85d8ad51">XTG_MSTERR_INTR_MINTREN_MASK</a>))</div>
<div class="ttc" id="xtrafgen__hw_8h_html_ac6e57b26c1f5674deb7c571dc319bf9e"><div class="ttname"><a href="xtrafgen__hw_8h.html#ac6e57b26c1f5674deb7c571dc319bf9e">XTrafGen_WriteReg</a></div><div class="ttdeci">#define XTrafGen_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">XTrafGen_WriteReg, writes Data to the register specified by RegOffset. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:424</div></div>
<div class="ttc" id="group__trafgen__v3__2_html_ga8549ea88039b3f646e33299b490b8904"><div class="ttname"><a href="group__trafgen__v3__2.html#ga8549ea88039b3f646e33299b490b8904">XTG_MSTERR_INTR_OFFSET</a></div><div class="ttdeci">#define XTG_MSTERR_INTR_OFFSET</div><div class="ttdoc">Master Err Interrupt Enable. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:90</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_a7f69f7e850cdf6eaeacb76be85d8ad51"><div class="ttname"><a href="xtrafgen__hw_8h.html#a7f69f7e850cdf6eaeacb76be85d8ad51">XTG_MSTERR_INTR_MINTREN_MASK</a></div><div class="ttdeci">#define XTG_MSTERR_INTR_MINTREN_MASK</div><div class="ttdoc">Master Err Interrupt Enable. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:214</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_affb7c95abd8cad50d7efa83f94ea3344"><div class="ttname"><a href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a></div><div class="ttdeci">#define XTrafGen_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...</div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:404</div></div>
</div><!-- fragment -->
<p>XTrafGen_MasterErrIntrDisable disables Global Master error bit. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Axi TrafGen instance to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__trafgen__v3__2.html#gab224de7e1fd0dcc9dc2627b625f81424" title="XTrafGen_MasterErrIntrDisable disables Global Master error bit. ">XTrafGen_MasterErrIntrDisable(XTrafGen *InstancePtr)</a> </dd></dl>

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      <table class="memname">
        <tr>
          <td class="memname">#define XTrafGen_MasterErrIntrEnable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xtrafgen__hw_8h.html#ac6e57b26c1f5674deb7c571dc319bf9e">XTrafGen_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress,  \</div>
<div class="line">                <a class="code" href="group__trafgen__v3__2.html#ga8549ea88039b3f646e33299b490b8904">XTG_MSTERR_INTR_OFFSET</a>, \</div>
<div class="line">                (<a class="code" href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                        <a class="code" href="group__trafgen__v3__2.html#ga8549ea88039b3f646e33299b490b8904">XTG_MSTERR_INTR_OFFSET</a>) |       \</div>
<div class="line">                        <a class="code" href="xtrafgen__hw_8h.html#a7f69f7e850cdf6eaeacb76be85d8ad51">XTG_MSTERR_INTR_MINTREN_MASK</a>))</div>
<div class="ttc" id="xtrafgen__hw_8h_html_ac6e57b26c1f5674deb7c571dc319bf9e"><div class="ttname"><a href="xtrafgen__hw_8h.html#ac6e57b26c1f5674deb7c571dc319bf9e">XTrafGen_WriteReg</a></div><div class="ttdeci">#define XTrafGen_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">XTrafGen_WriteReg, writes Data to the register specified by RegOffset. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:424</div></div>
<div class="ttc" id="group__trafgen__v3__2_html_ga8549ea88039b3f646e33299b490b8904"><div class="ttname"><a href="group__trafgen__v3__2.html#ga8549ea88039b3f646e33299b490b8904">XTG_MSTERR_INTR_OFFSET</a></div><div class="ttdeci">#define XTG_MSTERR_INTR_OFFSET</div><div class="ttdoc">Master Err Interrupt Enable. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:90</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_a7f69f7e850cdf6eaeacb76be85d8ad51"><div class="ttname"><a href="xtrafgen__hw_8h.html#a7f69f7e850cdf6eaeacb76be85d8ad51">XTG_MSTERR_INTR_MINTREN_MASK</a></div><div class="ttdeci">#define XTG_MSTERR_INTR_MINTREN_MASK</div><div class="ttdoc">Master Err Interrupt Enable. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:214</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_affb7c95abd8cad50d7efa83f94ea3344"><div class="ttname"><a href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a></div><div class="ttdeci">#define XTrafGen_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...</div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:404</div></div>
</div><!-- fragment -->
<p>XTrafGen_MasterErrIntrEnable enables Global Master error bit. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Axi TrafGen instance to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__trafgen__v3__2.html#ga154f34818edeb0858c445690fa4f8670" title="XTrafGen_MasterErrIntrEnable enables Global Master error bit. ">XTrafGen_MasterErrIntrEnable(XTrafGen *InstancePtr)</a> </dd></dl>

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          <td class="memname">#define XTrafGen_ReadConfigStatus</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress,  \</div>
<div class="line">        <a class="code" href="group__trafgen__v3__2.html#gadf7e15dfd4ecd23278ff780bf4369058">XTG_CFG_STS_OFFSET</a>))</div>
<div class="ttc" id="group__trafgen__v3__2_html_gadf7e15dfd4ecd23278ff780bf4369058"><div class="ttname"><a href="group__trafgen__v3__2.html#gadf7e15dfd4ecd23278ff780bf4369058">XTG_CFG_STS_OFFSET</a></div><div class="ttdeci">#define XTG_CFG_STS_OFFSET</div><div class="ttdoc">Config Status. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:91</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_affb7c95abd8cad50d7efa83f94ea3344"><div class="ttname"><a href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a></div><div class="ttdeci">#define XTrafGen_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...</div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:404</div></div>
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<p>XTrafGen_ReadConfigStatus reads Config status register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Axi TrafGen instance to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Config Status Register value</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__trafgen__v3__2.html#gad072536408b0e73e38978c57e0002c79" title="XTrafGen_ReadConfigStatus reads Config status register. ">XTrafGen_ReadConfigStatus(XTrafGen *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="group__trafgen__v3__2.html#ga4d40f6d5551836dab49e0d22e8d5e1eb">XTrafGen_CfgInitialize()</a>.</p>

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          <td class="memname">#define XTrafGen_ReadCoreRevision</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">((<a class="code" href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress,   \</div>
<div class="line">                <a class="code" href="group__trafgen__v3__2.html#ga2aee9e721b35ce512abb502ede5b8a06">XTG_MCNTL_OFFSET</a>) &amp; <a class="code" href="group__trafgen__v3__2.html#ga2197ba1e4ea908189bc7d77e70ba5a06">XTG_MCNTL_REV_MASK</a>) &gt;&gt; \</div>
<div class="line">                <a class="code" href="group__trafgen__v3__2.html#ga07d0697117d702e5a767bc8cc5083ea0">XTG_MCNTL_REV_SHIFT</a>)</div>
<div class="ttc" id="group__trafgen__v3__2_html_ga2197ba1e4ea908189bc7d77e70ba5a06"><div class="ttname"><a href="group__trafgen__v3__2.html#ga2197ba1e4ea908189bc7d77e70ba5a06">XTG_MCNTL_REV_MASK</a></div><div class="ttdeci">#define XTG_MCNTL_REV_MASK</div><div class="ttdoc">Core Revision Mask. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:118</div></div>
<div class="ttc" id="group__trafgen__v3__2_html_ga07d0697117d702e5a767bc8cc5083ea0"><div class="ttname"><a href="group__trafgen__v3__2.html#ga07d0697117d702e5a767bc8cc5083ea0">XTG_MCNTL_REV_SHIFT</a></div><div class="ttdeci">#define XTG_MCNTL_REV_SHIFT</div><div class="ttdoc">Core Rev shift. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:125</div></div>
<div class="ttc" id="group__trafgen__v3__2_html_ga2aee9e721b35ce512abb502ede5b8a06"><div class="ttname"><a href="group__trafgen__v3__2.html#ga2aee9e721b35ce512abb502ede5b8a06">XTG_MCNTL_OFFSET</a></div><div class="ttdeci">#define XTG_MCNTL_OFFSET</div><div class="ttdoc">Master Control. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:86</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_affb7c95abd8cad50d7efa83f94ea3344"><div class="ttname"><a href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a></div><div class="ttdeci">#define XTrafGen_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...</div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:404</div></div>
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<p>XTrafGen_ReadCoreRevision reads revision of core. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Axi TrafGen instance to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Core Revision Value</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u8 <a class="el" href="group__trafgen__v3__2.html#ga4d79e5e5aab48b68ee266961b89da00c" title="XTrafGen_ReadCoreRevision reads revision of core. ">XTrafGen_ReadCoreRevision(XTrafGen *InstancePtr)</a> </dd></dl>

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          <td class="memname">#define XTrafGen_ReadErrors</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress,    \</div>
<div class="line">                <a class="code" href="group__trafgen__v3__2.html#ga6d44ba5c998cf48c8162812f1b183cfa">XTG_ERR_STS_OFFSET</a>) &amp; <a class="code" href="group__trafgen__v3__2.html#gafdb598343bdb0bf2c6c5d29f8258f692">XTG_ERR_ALL_ERR_MASK</a>)</div>
<div class="ttc" id="group__trafgen__v3__2_html_gafdb598343bdb0bf2c6c5d29f8258f692"><div class="ttname"><a href="group__trafgen__v3__2.html#gafdb598343bdb0bf2c6c5d29f8258f692">XTG_ERR_ALL_ERR_MASK</a></div><div class="ttdeci">#define XTG_ERR_ALL_ERR_MASK</div><div class="ttdoc">All Errors Mask. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:163</div></div>
<div class="ttc" id="group__trafgen__v3__2_html_ga6d44ba5c998cf48c8162812f1b183cfa"><div class="ttname"><a href="group__trafgen__v3__2.html#ga6d44ba5c998cf48c8162812f1b183cfa">XTG_ERR_STS_OFFSET</a></div><div class="ttdeci">#define XTG_ERR_STS_OFFSET</div><div class="ttdoc">Error Status. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:88</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_affb7c95abd8cad50d7efa83f94ea3344"><div class="ttname"><a href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a></div><div class="ttdeci">#define XTrafGen_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...</div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:404</div></div>
</div><!-- fragment -->
<p>XTrafGen_ReadErrors read master and slave errors. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Axi TrafGen instance to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Both Master and Slave error value.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__trafgen__v3__2.html#ga20e311a5ca0e3aa3cce768d48a2bfb88" title="XTrafGen_ReadErrors read master and slave errors. ">XTrafGen_ReadErrors(XTrafGen *InstancePtr)</a> </dd></dl>

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          <td class="memname">#define XTrafGen_ReadIdWidth</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">((<a class="code" href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress,   \</div>
<div class="line">                <a class="code" href="group__trafgen__v3__2.html#ga2aee9e721b35ce512abb502ede5b8a06">XTG_MCNTL_OFFSET</a>) &amp; <a class="code" href="group__trafgen__v3__2.html#ga912b534ed07c85f5147d86a5125e6cd8">XTG_MCNTL_MSTID_MASK</a>) &gt;&gt;    \</div>
<div class="line">                <a class="code" href="group__trafgen__v3__2.html#gab849a5c24ef2753d38f62531ed5dcba9">XTG_MCNTL_MSTID_SHIFT</a>)</div>
<div class="ttc" id="group__trafgen__v3__2_html_ga912b534ed07c85f5147d86a5125e6cd8"><div class="ttname"><a href="group__trafgen__v3__2.html#ga912b534ed07c85f5147d86a5125e6cd8">XTG_MCNTL_MSTID_MASK</a></div><div class="ttdeci">#define XTG_MCNTL_MSTID_MASK</div><div class="ttdoc">M_ID_WIDTH Mask. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:119</div></div>
<div class="ttc" id="group__trafgen__v3__2_html_gab849a5c24ef2753d38f62531ed5dcba9"><div class="ttname"><a href="group__trafgen__v3__2.html#gab849a5c24ef2753d38f62531ed5dcba9">XTG_MCNTL_MSTID_SHIFT</a></div><div class="ttdeci">#define XTG_MCNTL_MSTID_SHIFT</div><div class="ttdoc">M_ID_WIDTH shift. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:126</div></div>
<div class="ttc" id="group__trafgen__v3__2_html_ga2aee9e721b35ce512abb502ede5b8a06"><div class="ttname"><a href="group__trafgen__v3__2.html#ga2aee9e721b35ce512abb502ede5b8a06">XTG_MCNTL_OFFSET</a></div><div class="ttdeci">#define XTG_MCNTL_OFFSET</div><div class="ttdoc">Master Control. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:86</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_affb7c95abd8cad50d7efa83f94ea3344"><div class="ttname"><a href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a></div><div class="ttdeci">#define XTrafGen_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...</div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:404</div></div>
</div><!-- fragment -->
<p>XTrafGen_ReadIdWidth reads M_ID_WIDTH. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Axi TrafGen instance to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Value of M_ID_WIDTH</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u8 <a class="el" href="group__trafgen__v3__2.html#ga1146dfb17253668f42cd6b2f679552cc" title="XTrafGen_ReadIdWidth reads M_ID_WIDTH. ">XTrafGen_ReadIdWidth(XTrafGen *InstancePtr)</a> </dd></dl>

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          <td class="memname">#define XTrafGen_ResetStreamingRandomLen</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="xtrafgen__hw_8h.html#ac6e57b26c1f5674deb7c571dc319bf9e">XTrafGen_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress,           \</div>
<div class="line">                <a class="code" href="group__trafgen__v3__2.html#ga0faa9082cff01c4e5e53bb957b69dae2">XTG_STREAM_CFG_OFFSET</a>,                                  \</div>
<div class="line">                (<a class="code" href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress,    \</div>
<div class="line">                <a class="code" href="group__trafgen__v3__2.html#ga0faa9082cff01c4e5e53bb957b69dae2">XTG_STREAM_CFG_OFFSET</a>) &amp; ~<a class="code" href="xtrafgen__hw_8h.html#ae44681fc73afbcdb7ae0015719f8ac47">XTG_STREAM_CFG_RANDL_MASK</a>)))</div>
<div class="ttc" id="xtrafgen__hw_8h_html_ac6e57b26c1f5674deb7c571dc319bf9e"><div class="ttname"><a href="xtrafgen__hw_8h.html#ac6e57b26c1f5674deb7c571dc319bf9e">XTrafGen_WriteReg</a></div><div class="ttdeci">#define XTrafGen_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">XTrafGen_WriteReg, writes Data to the register specified by RegOffset. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:424</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_ae44681fc73afbcdb7ae0015719f8ac47"><div class="ttname"><a href="xtrafgen__hw_8h.html#ae44681fc73afbcdb7ae0015719f8ac47">XTG_STREAM_CFG_RANDL_MASK</a></div><div class="ttdeci">#define XTG_STREAM_CFG_RANDL_MASK</div><div class="ttdoc">Random Length Mask. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:264</div></div>
<div class="ttc" id="group__trafgen__v3__2_html_ga0faa9082cff01c4e5e53bb957b69dae2"><div class="ttname"><a href="group__trafgen__v3__2.html#ga0faa9082cff01c4e5e53bb957b69dae2">XTG_STREAM_CFG_OFFSET</a></div><div class="ttdeci">#define XTG_STREAM_CFG_OFFSET</div><div class="ttdoc">Streaming Config. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:93</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_affb7c95abd8cad50d7efa83f94ea3344"><div class="ttname"><a href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a></div><div class="ttdeci">#define XTrafGen_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...</div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:404</div></div>
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<p>XTrafGen_ResetStreamingRandomLen resets the random transaction length for AxiTrafGen in Streaming Mode. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Axi TrafGen instance to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__trafgen__v3__2.html#ga5481f14f30231fcf80dafa2b77f6e8a3" title="XTrafGen_ResetStreamingRandomLen resets the random transaction length for AxiTrafGen in Streaming Mod...">XTrafGen_ResetStreamingRandomLen(XTrafGen *InstancePtr)</a> </dd></dl>

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          <td class="memname">#define XTrafGen_SetStaticBurstLen</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Value&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="xtrafgen__hw_8h.html#ac6e57b26c1f5674deb7c571dc319bf9e">XTrafGen_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress,   \</div>
<div class="line">                <a class="code" href="group__trafgen__v3__2.html#ga1813133f0d9bd28861fac1a854137411">XTG_STATIC_LEN_OFFSET</a>,Value))</div>
<div class="ttc" id="xtrafgen__hw_8h_html_ac6e57b26c1f5674deb7c571dc319bf9e"><div class="ttname"><a href="xtrafgen__hw_8h.html#ac6e57b26c1f5674deb7c571dc319bf9e">XTrafGen_WriteReg</a></div><div class="ttdeci">#define XTrafGen_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">XTrafGen_WriteReg, writes Data to the register specified by RegOffset. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:424</div></div>
<div class="ttc" id="group__trafgen__v3__2_html_ga1813133f0d9bd28861fac1a854137411"><div class="ttname"><a href="group__trafgen__v3__2.html#ga1813133f0d9bd28861fac1a854137411">XTG_STATIC_LEN_OFFSET</a></div><div class="ttdeci">#define XTG_STATIC_LEN_OFFSET</div><div class="ttdoc">Static Length. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:100</div></div>
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<p>XTrafGen_SetStaticBurstLen Configures the Burst Length for AxiTrafGen In Static Mode. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Axi TrafGen instance to be worked on. </td></tr>
    <tr><td class="paramname">Value</td><td>is the Burst length to set in the Static length register.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void XTrafGen_SetStaticBurstLen(<a class="el" href="struct_x_traf_gen.html" title="The XTrafGen driver instance data. ">XTrafGen</a> *InstancePtr, u32 Value) </dd></dl>

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          <td class="memname">#define XTrafGen_SetStaticTransferDone</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xtrafgen__hw_8h.html#ac6e57b26c1f5674deb7c571dc319bf9e">XTrafGen_WriteReg</a>(InstancePtr-&gt;Config.BaseAddress,              \</div>
<div class="line">                <a class="code" href="group__trafgen__v3__2.html#gafee2ca23e3fc2ed4964740ba69dde023">XTG_STATIC_CNTL_OFFSET</a>,                                 \</div>
<div class="line">                (<a class="code" href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress,    \</div>
<div class="line">                <a class="code" href="group__trafgen__v3__2.html#gafee2ca23e3fc2ed4964740ba69dde023">XTG_STATIC_CNTL_OFFSET</a>) | <a class="code" href="xtrafgen__hw_8h.html#ae82296e2d81edb5da14c813e36b604cc">XTG_STATIC_CNTL_TD_MASK</a>))</div>
<div class="ttc" id="xtrafgen__hw_8h_html_ac6e57b26c1f5674deb7c571dc319bf9e"><div class="ttname"><a href="xtrafgen__hw_8h.html#ac6e57b26c1f5674deb7c571dc319bf9e">XTrafGen_WriteReg</a></div><div class="ttdeci">#define XTrafGen_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">XTrafGen_WriteReg, writes Data to the register specified by RegOffset. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:424</div></div>
<div class="ttc" id="group__trafgen__v3__2_html_gafee2ca23e3fc2ed4964740ba69dde023"><div class="ttname"><a href="group__trafgen__v3__2.html#gafee2ca23e3fc2ed4964740ba69dde023">XTG_STATIC_CNTL_OFFSET</a></div><div class="ttdeci">#define XTG_STATIC_CNTL_OFFSET</div><div class="ttdoc">Static Mode Register Descrptions. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:99</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_ae82296e2d81edb5da14c813e36b604cc"><div class="ttname"><a href="xtrafgen__hw_8h.html#ae82296e2d81edb5da14c813e36b604cc">XTG_STATIC_CNTL_TD_MASK</a></div><div class="ttdeci">#define XTG_STATIC_CNTL_TD_MASK</div><div class="ttdoc">Transfer Done Mask. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:288</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_affb7c95abd8cad50d7efa83f94ea3344"><div class="ttname"><a href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a></div><div class="ttdeci">#define XTrafGen_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...</div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:404</div></div>
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<p>XTrafGen_SetStaticTransferDone sets the Transfer done bit in Control register When AxiTrafGen is Configured in Static Mode. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Axi TrafGen instance to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__trafgen__v3__2.html#gacba2dd56bfff034a966b81a2103a6bb4" title="XTrafGen_SetStaticTransferDone sets the Transfer done bit in Control register When AxiTrafGen is Conf...">XTrafGen_SetStaticTransferDone(XTrafGen *InstancePtr)</a> </dd></dl>

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<a class="anchor" id="ga3beeeec32649b7df9c049a6b08daa55a"></a>
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          <td class="memname">#define XTrafGen_SetStreamingProgDelay</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Value&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="xtrafgen__hw_8h.html#ac6e57b26c1f5674deb7c571dc319bf9e">XTrafGen_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress,   \</div>
<div class="line">                <a class="code" href="group__trafgen__v3__2.html#ga0faa9082cff01c4e5e53bb957b69dae2">XTG_STREAM_CFG_OFFSET</a>,  \</div>
<div class="line">                (<a class="code" href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                 <a class="code" href="group__trafgen__v3__2.html#ga0faa9082cff01c4e5e53bb957b69dae2">XTG_STREAM_CFG_OFFSET</a>)|(Value &lt;&lt; <a class="code" href="xtrafgen__hw_8h.html#aea7d215adbbf69b18fac485e2d150bd9">XTG_STREAM_CFG_PDLY_SHIFT</a>)) \</div>
<div class="line">                 &amp; <a class="code" href="xtrafgen__hw_8h.html#a490ccc5cf897e6daf0e403fdb5028cc8">XTG_STREAM_CFG_PDLY_MASK</a>))</div>
<div class="ttc" id="xtrafgen__hw_8h_html_ac6e57b26c1f5674deb7c571dc319bf9e"><div class="ttname"><a href="xtrafgen__hw_8h.html#ac6e57b26c1f5674deb7c571dc319bf9e">XTrafGen_WriteReg</a></div><div class="ttdeci">#define XTrafGen_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">XTrafGen_WriteReg, writes Data to the register specified by RegOffset. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:424</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_aea7d215adbbf69b18fac485e2d150bd9"><div class="ttname"><a href="xtrafgen__hw_8h.html#aea7d215adbbf69b18fac485e2d150bd9">XTG_STREAM_CFG_PDLY_SHIFT</a></div><div class="ttdeci">#define XTG_STREAM_CFG_PDLY_SHIFT</div><div class="ttdoc">Programmable Delay Shift. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:255</div></div>
<div class="ttc" id="group__trafgen__v3__2_html_ga0faa9082cff01c4e5e53bb957b69dae2"><div class="ttname"><a href="group__trafgen__v3__2.html#ga0faa9082cff01c4e5e53bb957b69dae2">XTG_STREAM_CFG_OFFSET</a></div><div class="ttdeci">#define XTG_STREAM_CFG_OFFSET</div><div class="ttdoc">Streaming Config. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:93</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_a490ccc5cf897e6daf0e403fdb5028cc8"><div class="ttname"><a href="xtrafgen__hw_8h.html#a490ccc5cf897e6daf0e403fdb5028cc8">XTG_STREAM_CFG_PDLY_MASK</a></div><div class="ttdeci">#define XTG_STREAM_CFG_PDLY_MASK</div><div class="ttdoc">Programmable Delay Mask. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:256</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_affb7c95abd8cad50d7efa83f94ea3344"><div class="ttname"><a href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a></div><div class="ttdeci">#define XTrafGen_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...</div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:404</div></div>
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<p>XTrafGen_SetStreamingProgDelay Configures the Programmable Delay for AxiTrafGen in Streaming Mode. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Axi TrafGen instance to be worked on. </td></tr>
    <tr><td class="paramname">Value</td><td>is the value that's need to be configure in the Stream Config Register.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void XTrafGen_SetStreamingProgDelay(<a class="el" href="struct_x_traf_gen.html" title="The XTrafGen driver instance data. ">XTrafGen</a> *InstancePtr, u32 Value) </dd></dl>

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<a class="anchor" id="gaab0a135f1ad92788eeb768cfe26b74b3"></a>
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          <td class="memname">#define XTrafGen_SetStreamingRandomLen</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Value&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="xtrafgen__hw_8h.html#ac6e57b26c1f5674deb7c571dc319bf9e">XTrafGen_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress,           \</div>
<div class="line">                <a class="code" href="group__trafgen__v3__2.html#ga0faa9082cff01c4e5e53bb957b69dae2">XTG_STREAM_CFG_OFFSET</a>,                                  \</div>
<div class="line">                (<a class="code" href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress,    \</div>
<div class="line">                <a class="code" href="group__trafgen__v3__2.html#ga0faa9082cff01c4e5e53bb957b69dae2">XTG_STREAM_CFG_OFFSET</a>) | Value)))</div>
<div class="ttc" id="xtrafgen__hw_8h_html_ac6e57b26c1f5674deb7c571dc319bf9e"><div class="ttname"><a href="xtrafgen__hw_8h.html#ac6e57b26c1f5674deb7c571dc319bf9e">XTrafGen_WriteReg</a></div><div class="ttdeci">#define XTrafGen_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">XTrafGen_WriteReg, writes Data to the register specified by RegOffset. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:424</div></div>
<div class="ttc" id="group__trafgen__v3__2_html_ga0faa9082cff01c4e5e53bb957b69dae2"><div class="ttname"><a href="group__trafgen__v3__2.html#ga0faa9082cff01c4e5e53bb957b69dae2">XTG_STREAM_CFG_OFFSET</a></div><div class="ttdeci">#define XTG_STREAM_CFG_OFFSET</div><div class="ttdoc">Streaming Config. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:93</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_affb7c95abd8cad50d7efa83f94ea3344"><div class="ttname"><a href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a></div><div class="ttdeci">#define XTrafGen_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...</div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:404</div></div>
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<p>XTrafGen_SetStreamingRandomLen Configures the random transaction length for AxiTrafGen in Streaming Mode. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Axi TrafGen instance to be worked on. </td></tr>
    <tr><td class="paramname">Value</td><td>is the random length that's need to be Configure in the Streaming Config register.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void XTrafGen_SetStreamingRandomLen(<a class="el" href="struct_x_traf_gen.html" title="The XTrafGen driver instance data. ">XTrafGen</a> *InstancePtr, u32 Value) </dd></dl>

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<a class="anchor" id="gae5372945bcdfa008f7daf48f97edbd7f"></a>
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      <table class="memname">
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          <td class="memname">#define XTrafGen_SetStreamingTdestPort</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Value&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="xtrafgen__hw_8h.html#ac6e57b26c1f5674deb7c571dc319bf9e">XTrafGen_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress,  \</div>
<div class="line">                <a class="code" href="group__trafgen__v3__2.html#ga0faa9082cff01c4e5e53bb957b69dae2">XTG_STREAM_CFG_OFFSET</a>,  \</div>
<div class="line">                (<a class="code" href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                <a class="code" href="group__trafgen__v3__2.html#ga0faa9082cff01c4e5e53bb957b69dae2">XTG_STREAM_CFG_OFFSET</a>)|(Value &lt;&lt; <a class="code" href="xtrafgen__hw_8h.html#acf47f8d5a9f92da3d0d5b4fd6be627a6">XTG_STREAM_CFG_TDEST_SHIFT</a>)) \</div>
<div class="line">                &amp; <a class="code" href="xtrafgen__hw_8h.html#a27be0cf2c90513010b73b0b8db1163dc">XTG_STREAM_CFG_TDEST_MASK</a>))</div>
<div class="ttc" id="xtrafgen__hw_8h_html_ac6e57b26c1f5674deb7c571dc319bf9e"><div class="ttname"><a href="xtrafgen__hw_8h.html#ac6e57b26c1f5674deb7c571dc319bf9e">XTrafGen_WriteReg</a></div><div class="ttdeci">#define XTrafGen_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">XTrafGen_WriteReg, writes Data to the register specified by RegOffset. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:424</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_acf47f8d5a9f92da3d0d5b4fd6be627a6"><div class="ttname"><a href="xtrafgen__hw_8h.html#acf47f8d5a9f92da3d0d5b4fd6be627a6">XTG_STREAM_CFG_TDEST_SHIFT</a></div><div class="ttdeci">#define XTG_STREAM_CFG_TDEST_SHIFT</div><div class="ttdoc">TDEST PORT Shift. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:258</div></div>
<div class="ttc" id="group__trafgen__v3__2_html_ga0faa9082cff01c4e5e53bb957b69dae2"><div class="ttname"><a href="group__trafgen__v3__2.html#ga0faa9082cff01c4e5e53bb957b69dae2">XTG_STREAM_CFG_OFFSET</a></div><div class="ttdeci">#define XTG_STREAM_CFG_OFFSET</div><div class="ttdoc">Streaming Config. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:93</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_a27be0cf2c90513010b73b0b8db1163dc"><div class="ttname"><a href="xtrafgen__hw_8h.html#a27be0cf2c90513010b73b0b8db1163dc">XTG_STREAM_CFG_TDEST_MASK</a></div><div class="ttdeci">#define XTG_STREAM_CFG_TDEST_MASK</div><div class="ttdoc">TDEST PORT Mask. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:259</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_affb7c95abd8cad50d7efa83f94ea3344"><div class="ttname"><a href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a></div><div class="ttdeci">#define XTrafGen_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...</div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:404</div></div>
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<p>XTrafGen_SetStreamingTdestPort Configures the Value to drive on TDEST port for Axi TrafGen in Streaming Mode. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Axi TrafGen instance to be worked on. </td></tr>
    <tr><td class="paramname">Value</td><td>is the Port value that's need to be set.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void XTrafGen_SetStreamingTdestPort(<a class="el" href="struct_x_traf_gen.html" title="The XTrafGen driver instance data. ">XTrafGen</a> *InstancePtr, u8 Value) </dd></dl>

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<a class="anchor" id="ga90d0e4161092c15a1ca821f97cdd7a4b"></a>
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          <td class="memname">#define XTrafGen_SetStreamingTransCnt</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Value&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="xtrafgen__hw_8h.html#ac6e57b26c1f5674deb7c571dc319bf9e">XTrafGen_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress,   \</div>
<div class="line">                <a class="code" href="group__trafgen__v3__2.html#ga476caa717b80c4d276d7ff98aae5f3ca">XTG_STREAM_TL_OFFSET</a>,   \</div>
<div class="line">                (<a class="code" href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress,    \</div>
<div class="line">                 <a class="code" href="group__trafgen__v3__2.html#ga476caa717b80c4d276d7ff98aae5f3ca">XTG_STREAM_TL_OFFSET</a>) |((Value &lt;&lt; <a class="code" href="xtrafgen__hw_8h.html#a826017ee56ef1171a4d132dc12ca8341">XTG_STREAM_TL_TCNT_SHIFT</a>) \</div>
<div class="line">                 &amp; <a class="code" href="xtrafgen__hw_8h.html#a556bcb7b08d4170167ee65c08c7a0ebe">XTG_STREAM_TL_TCNT_MASK</a>))))</div>
<div class="ttc" id="xtrafgen__hw_8h_html_ac6e57b26c1f5674deb7c571dc319bf9e"><div class="ttname"><a href="xtrafgen__hw_8h.html#ac6e57b26c1f5674deb7c571dc319bf9e">XTrafGen_WriteReg</a></div><div class="ttdeci">#define XTrafGen_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">XTrafGen_WriteReg, writes Data to the register specified by RegOffset. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:424</div></div>
<div class="ttc" id="group__trafgen__v3__2_html_ga476caa717b80c4d276d7ff98aae5f3ca"><div class="ttname"><a href="group__trafgen__v3__2.html#ga476caa717b80c4d276d7ff98aae5f3ca">XTG_STREAM_TL_OFFSET</a></div><div class="ttdeci">#define XTG_STREAM_TL_OFFSET</div><div class="ttdoc">Streaming Transfer Length. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:94</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_a826017ee56ef1171a4d132dc12ca8341"><div class="ttname"><a href="xtrafgen__hw_8h.html#a826017ee56ef1171a4d132dc12ca8341">XTG_STREAM_TL_TCNT_SHIFT</a></div><div class="ttdeci">#define XTG_STREAM_TL_TCNT_SHIFT</div><div class="ttdoc">Transfer Count Shift. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:273</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_a556bcb7b08d4170167ee65c08c7a0ebe"><div class="ttname"><a href="xtrafgen__hw_8h.html#a556bcb7b08d4170167ee65c08c7a0ebe">XTG_STREAM_TL_TCNT_MASK</a></div><div class="ttdeci">#define XTG_STREAM_TL_TCNT_MASK</div><div class="ttdoc">Transfer Count Mask. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:274</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_affb7c95abd8cad50d7efa83f94ea3344"><div class="ttname"><a href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a></div><div class="ttdeci">#define XTrafGen_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...</div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:404</div></div>
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<p>XTrafGen_SetStreamingTransCnt Configures the transfer count for AxiTrafGen in Streaming Mode. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Axi TrafGen instance to be worked on. </td></tr>
    <tr><td class="paramname">Value</td><td>is the transfer length that needs to be configured in Transfer length register.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void XTrafGen_SetStreamingTransCnt(<a class="el" href="struct_x_traf_gen.html" title="The XTrafGen driver instance data. ">XTrafGen</a> *InstancePtr, u32 Value) </dd></dl>

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          <td class="memname">#define XTrafGen_SetStreamingTransferDone</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xtrafgen__hw_8h.html#ac6e57b26c1f5674deb7c571dc319bf9e">XTrafGen_WriteReg</a>(InstancePtr-&gt;Config.BaseAddress,   \</div>
<div class="line">                <a class="code" href="group__trafgen__v3__2.html#gadad67dedb6f0b5c0e7aed2e0d62e08eb">XTG_STREAM_CNTL_OFFSET</a>,                         \</div>
<div class="line">                (<a class="code" href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                <a class="code" href="group__trafgen__v3__2.html#gadad67dedb6f0b5c0e7aed2e0d62e08eb">XTG_STREAM_CNTL_OFFSET</a>) | <a class="code" href="xtrafgen__hw_8h.html#a4b0674a7c9f7879bf6462860641b4d89">XTG_STREAM_CNTL_TD_MASK</a>))</div>
<div class="ttc" id="xtrafgen__hw_8h_html_ac6e57b26c1f5674deb7c571dc319bf9e"><div class="ttname"><a href="xtrafgen__hw_8h.html#ac6e57b26c1f5674deb7c571dc319bf9e">XTrafGen_WriteReg</a></div><div class="ttdeci">#define XTrafGen_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">XTrafGen_WriteReg, writes Data to the register specified by RegOffset. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:424</div></div>
<div class="ttc" id="group__trafgen__v3__2_html_gadad67dedb6f0b5c0e7aed2e0d62e08eb"><div class="ttname"><a href="group__trafgen__v3__2.html#gadad67dedb6f0b5c0e7aed2e0d62e08eb">XTG_STREAM_CNTL_OFFSET</a></div><div class="ttdeci">#define XTG_STREAM_CNTL_OFFSET</div><div class="ttdoc">Streaming Control. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:92</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_a4b0674a7c9f7879bf6462860641b4d89"><div class="ttname"><a href="xtrafgen__hw_8h.html#a4b0674a7c9f7879bf6462860641b4d89">XTG_STREAM_CNTL_TD_MASK</a></div><div class="ttdeci">#define XTG_STREAM_CNTL_TD_MASK</div><div class="ttdoc">Transfer Done Mask. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:244</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_affb7c95abd8cad50d7efa83f94ea3344"><div class="ttname"><a href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a></div><div class="ttdeci">#define XTrafGen_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...</div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:404</div></div>
</div><!-- fragment -->
<p>XTrafGen_SetTransferDone sets the Transfer done bit in Control register When AxiTrafGen is Configured in Streaming Mode. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Axi TrafGen instance to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__trafgen__v3__2.html#gaee4aa3d826f692264c3735a00c29aa47" title="XTrafGen_SetTransferDone sets the Transfer done bit in Control register When AxiTrafGen is Configured...">XTrafGen_SetStreamingTransferDone(XTrafGen *InstancePtr)</a> </dd></dl>

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<a class="anchor" id="gae7e5d3e4f6de43f247a5f52dbade8deb"></a>
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<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTrafGen_SetStreamingTransLen</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Value&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="xtrafgen__hw_8h.html#ac6e57b26c1f5674deb7c571dc319bf9e">XTrafGen_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress,           \</div>
<div class="line">                <a class="code" href="group__trafgen__v3__2.html#ga476caa717b80c4d276d7ff98aae5f3ca">XTG_STREAM_TL_OFFSET</a>,                                   \</div>
<div class="line">                (<a class="code" href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress,    \</div>
<div class="line">                <a class="code" href="group__trafgen__v3__2.html#ga476caa717b80c4d276d7ff98aae5f3ca">XTG_STREAM_TL_OFFSET</a>) | Value)))</div>
<div class="ttc" id="xtrafgen__hw_8h_html_ac6e57b26c1f5674deb7c571dc319bf9e"><div class="ttname"><a href="xtrafgen__hw_8h.html#ac6e57b26c1f5674deb7c571dc319bf9e">XTrafGen_WriteReg</a></div><div class="ttdeci">#define XTrafGen_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">XTrafGen_WriteReg, writes Data to the register specified by RegOffset. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:424</div></div>
<div class="ttc" id="group__trafgen__v3__2_html_ga476caa717b80c4d276d7ff98aae5f3ca"><div class="ttname"><a href="group__trafgen__v3__2.html#ga476caa717b80c4d276d7ff98aae5f3ca">XTG_STREAM_TL_OFFSET</a></div><div class="ttdeci">#define XTG_STREAM_TL_OFFSET</div><div class="ttdoc">Streaming Transfer Length. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:94</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_affb7c95abd8cad50d7efa83f94ea3344"><div class="ttname"><a href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a></div><div class="ttdeci">#define XTrafGen_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...</div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:404</div></div>
</div><!-- fragment -->
<p>XTrafGen_SetStreamingTransLen Configures the length of transaction for AxiTrafGen in Streaming Mode. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Axi TrafGen instance to be worked on. </td></tr>
    <tr><td class="paramname">Value</td><td>is the transfer length to set in the transfer length Register.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void XTrafGen_SetStreamingTransLen(<a class="el" href="struct_x_traf_gen.html" title="The XTrafGen driver instance data. ">XTrafGen</a> *InstancePtr, u32 Value) </dd></dl>

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          <td class="memname">#define XTrafGen_SlaveErrIntrDisable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xtrafgen__hw_8h.html#ac6e57b26c1f5674deb7c571dc319bf9e">XTrafGen_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress,  \</div>
<div class="line">                <a class="code" href="group__trafgen__v3__2.html#ga16ab165b5d7fd7c84206606b1bc2dcfa">XTG_SCNTL_OFFSET</a>, \</div>
<div class="line">                (<a class="code" href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                        <a class="code" href="group__trafgen__v3__2.html#ga16ab165b5d7fd7c84206606b1bc2dcfa">XTG_SCNTL_OFFSET</a>) &amp;     \</div>
<div class="line">                        ~<a class="code" href="group__trafgen__v3__2.html#gab3fd9e680a247d1ad78ba6cab9b061fb">XTG_SCNTL_ERREN_MASK</a>))</div>
<div class="ttc" id="xtrafgen__hw_8h_html_ac6e57b26c1f5674deb7c571dc319bf9e"><div class="ttname"><a href="xtrafgen__hw_8h.html#ac6e57b26c1f5674deb7c571dc319bf9e">XTrafGen_WriteReg</a></div><div class="ttdeci">#define XTrafGen_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">XTrafGen_WriteReg, writes Data to the register specified by RegOffset. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:424</div></div>
<div class="ttc" id="group__trafgen__v3__2_html_ga16ab165b5d7fd7c84206606b1bc2dcfa"><div class="ttname"><a href="group__trafgen__v3__2.html#ga16ab165b5d7fd7c84206606b1bc2dcfa">XTG_SCNTL_OFFSET</a></div><div class="ttdeci">#define XTG_SCNTL_OFFSET</div><div class="ttdoc">Slave Control. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:87</div></div>
<div class="ttc" id="group__trafgen__v3__2_html_gab3fd9e680a247d1ad78ba6cab9b061fb"><div class="ttname"><a href="group__trafgen__v3__2.html#gab3fd9e680a247d1ad78ba6cab9b061fb">XTG_SCNTL_ERREN_MASK</a></div><div class="ttdeci">#define XTG_SCNTL_ERREN_MASK</div><div class="ttdoc">Slv Error Interrupt Enable. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:146</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_affb7c95abd8cad50d7efa83f94ea3344"><div class="ttname"><a href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a></div><div class="ttdeci">#define XTrafGen_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...</div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:404</div></div>
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<p>XTrafGen_SlaveErrIntrDisable disables Global Slave error bit. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Axi TrafGen instance to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__trafgen__v3__2.html#gaa4b8bcf25ed401a3debc9665db06dfef" title="XTrafGen_SlaveErrIntrDisable disables Global Slave error bit. ">XTrafGen_SlaveErrIntrDisable(XTrafGen *InstancePtr)</a> </dd></dl>

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<a class="anchor" id="ga298a1b459b4552cb79b4a2da8d3a1845"></a>
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          <td class="memname">#define XTrafGen_SlaveErrIntrEnable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xtrafgen__hw_8h.html#ac6e57b26c1f5674deb7c571dc319bf9e">XTrafGen_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress,  \</div>
<div class="line">                <a class="code" href="group__trafgen__v3__2.html#ga16ab165b5d7fd7c84206606b1bc2dcfa">XTG_SCNTL_OFFSET</a>, \</div>
<div class="line">                (<a class="code" href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                        <a class="code" href="group__trafgen__v3__2.html#ga16ab165b5d7fd7c84206606b1bc2dcfa">XTG_SCNTL_OFFSET</a>) | <a class="code" href="group__trafgen__v3__2.html#gab3fd9e680a247d1ad78ba6cab9b061fb">XTG_SCNTL_ERREN_MASK</a>))</div>
<div class="ttc" id="xtrafgen__hw_8h_html_ac6e57b26c1f5674deb7c571dc319bf9e"><div class="ttname"><a href="xtrafgen__hw_8h.html#ac6e57b26c1f5674deb7c571dc319bf9e">XTrafGen_WriteReg</a></div><div class="ttdeci">#define XTrafGen_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">XTrafGen_WriteReg, writes Data to the register specified by RegOffset. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:424</div></div>
<div class="ttc" id="group__trafgen__v3__2_html_ga16ab165b5d7fd7c84206606b1bc2dcfa"><div class="ttname"><a href="group__trafgen__v3__2.html#ga16ab165b5d7fd7c84206606b1bc2dcfa">XTG_SCNTL_OFFSET</a></div><div class="ttdeci">#define XTG_SCNTL_OFFSET</div><div class="ttdoc">Slave Control. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:87</div></div>
<div class="ttc" id="group__trafgen__v3__2_html_gab3fd9e680a247d1ad78ba6cab9b061fb"><div class="ttname"><a href="group__trafgen__v3__2.html#gab3fd9e680a247d1ad78ba6cab9b061fb">XTG_SCNTL_ERREN_MASK</a></div><div class="ttdeci">#define XTG_SCNTL_ERREN_MASK</div><div class="ttdoc">Slv Error Interrupt Enable. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:146</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_affb7c95abd8cad50d7efa83f94ea3344"><div class="ttname"><a href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a></div><div class="ttdeci">#define XTrafGen_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...</div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:404</div></div>
</div><!-- fragment -->
<p>XTrafGen_SlaveErrIntrEnable enables Global Slave error bit. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Axi TrafGen instance to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__trafgen__v3__2.html#ga298a1b459b4552cb79b4a2da8d3a1845" title="XTrafGen_SlaveErrIntrEnable enables Global Slave error bit. ">XTrafGen_SlaveErrIntrEnable(XTrafGen *InstancePtr)</a> </dd></dl>

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          <td class="memname">#define XTrafGen_StartMasterLogic</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xtrafgen__hw_8h.html#ac6e57b26c1f5674deb7c571dc319bf9e">XTrafGen_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress,    \</div>
<div class="line">                <a class="code" href="group__trafgen__v3__2.html#ga2aee9e721b35ce512abb502ede5b8a06">XTG_MCNTL_OFFSET</a>,       \</div>
<div class="line">                (<a class="code" href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress,    \</div>
<div class="line">                        <a class="code" href="group__trafgen__v3__2.html#ga2aee9e721b35ce512abb502ede5b8a06">XTG_MCNTL_OFFSET</a>) | <a class="code" href="group__trafgen__v3__2.html#gaf8fafcd0c1061fbf9d6d61680a251309">XTG_MCNTL_MSTEN_MASK</a>))</div>
<div class="ttc" id="xtrafgen__hw_8h_html_ac6e57b26c1f5674deb7c571dc319bf9e"><div class="ttname"><a href="xtrafgen__hw_8h.html#ac6e57b26c1f5674deb7c571dc319bf9e">XTrafGen_WriteReg</a></div><div class="ttdeci">#define XTrafGen_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">XTrafGen_WriteReg, writes Data to the register specified by RegOffset. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:424</div></div>
<div class="ttc" id="group__trafgen__v3__2_html_gaf8fafcd0c1061fbf9d6d61680a251309"><div class="ttname"><a href="group__trafgen__v3__2.html#gaf8fafcd0c1061fbf9d6d61680a251309">XTG_MCNTL_MSTEN_MASK</a></div><div class="ttdeci">#define XTG_MCNTL_MSTEN_MASK</div><div class="ttdoc">Master Logic Enable Mask. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:120</div></div>
<div class="ttc" id="group__trafgen__v3__2_html_ga2aee9e721b35ce512abb502ede5b8a06"><div class="ttname"><a href="group__trafgen__v3__2.html#ga2aee9e721b35ce512abb502ede5b8a06">XTG_MCNTL_OFFSET</a></div><div class="ttdeci">#define XTG_MCNTL_OFFSET</div><div class="ttdoc">Master Control. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:86</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_affb7c95abd8cad50d7efa83f94ea3344"><div class="ttname"><a href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a></div><div class="ttdeci">#define XTrafGen_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...</div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:404</div></div>
</div><!-- fragment -->
<p>XTrafGen_StartMasterLogic starts traffic generator master logic. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Axi TrafGen instance to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__trafgen__v3__2.html#gaf55f0066544c5ca956f2775e2927851d" title="XTrafGen_StartMasterLogic starts traffic generator master logic. ">XTrafGen_StartMasterLogic(XTrafGen *InstancePtr)</a> </dd></dl>

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        <tr>
          <td class="memname">#define XTrafGen_StaticDisable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="xtrafgen__hw_8h.html#ac6e57b26c1f5674deb7c571dc319bf9e">XTrafGen_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress,           \</div>
<div class="line">                <a class="code" href="group__trafgen__v3__2.html#gafee2ca23e3fc2ed4964740ba69dde023">XTG_STATIC_CNTL_OFFSET</a>,                                 \</div>
<div class="line">                (<a class="code" href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress,    \</div>
<div class="line">                 <a class="code" href="group__trafgen__v3__2.html#gafee2ca23e3fc2ed4964740ba69dde023">XTG_STATIC_CNTL_OFFSET</a>) &amp; <a class="code" href="xtrafgen__hw_8h.html#a4955ccf9832cc09dd5f05b54f49104dd">XTG_STATIC_CNTL_RESET_MASK</a>)))</div>
<div class="ttc" id="xtrafgen__hw_8h_html_ac6e57b26c1f5674deb7c571dc319bf9e"><div class="ttname"><a href="xtrafgen__hw_8h.html#ac6e57b26c1f5674deb7c571dc319bf9e">XTrafGen_WriteReg</a></div><div class="ttdeci">#define XTrafGen_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">XTrafGen_WriteReg, writes Data to the register specified by RegOffset. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:424</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_a4955ccf9832cc09dd5f05b54f49104dd"><div class="ttname"><a href="xtrafgen__hw_8h.html#a4955ccf9832cc09dd5f05b54f49104dd">XTG_STATIC_CNTL_RESET_MASK</a></div><div class="ttdeci">#define XTG_STATIC_CNTL_RESET_MASK</div><div class="ttdoc">Static Disable Mask. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:291</div></div>
<div class="ttc" id="group__trafgen__v3__2_html_gafee2ca23e3fc2ed4964740ba69dde023"><div class="ttname"><a href="group__trafgen__v3__2.html#gafee2ca23e3fc2ed4964740ba69dde023">XTG_STATIC_CNTL_OFFSET</a></div><div class="ttdeci">#define XTG_STATIC_CNTL_OFFSET</div><div class="ttdoc">Static Mode Register Descrptions. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:99</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_affb7c95abd8cad50d7efa83f94ea3344"><div class="ttname"><a href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a></div><div class="ttdeci">#define XTrafGen_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...</div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:404</div></div>
</div><!-- fragment -->
<p>XTrafGen_StaticDisable disables the traffic genration on the Axi TrafGen when the core is configured in Static Mode. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Axi TrafGen instance to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__trafgen__v3__2.html#gab54737e40a38ba5316b487a045568b11" title="XTrafGen_StaticDisable disables the traffic genration on the Axi TrafGen when the core is configured ...">XTrafGen_StaticDisable(XTrafGen *InstancePtr)</a> </dd></dl>

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<a class="anchor" id="ga21218c919ca08e948a557334a8f1ba95"></a>
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        <tr>
          <td class="memname">#define XTrafGen_StaticEnable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="xtrafgen__hw_8h.html#ac6e57b26c1f5674deb7c571dc319bf9e">XTrafGen_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress,           \</div>
<div class="line">                <a class="code" href="group__trafgen__v3__2.html#gafee2ca23e3fc2ed4964740ba69dde023">XTG_STATIC_CNTL_OFFSET</a>,                                 \</div>
<div class="line">                (<a class="code" href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress,    \</div>
<div class="line">                 <a class="code" href="group__trafgen__v3__2.html#gafee2ca23e3fc2ed4964740ba69dde023">XTG_STATIC_CNTL_OFFSET</a>) | <a class="code" href="xtrafgen__hw_8h.html#a820c08467cb0fc69af91e8747bf52199">XTG_STATIC_CNTL_STEN_MASK</a>)))</div>
<div class="ttc" id="xtrafgen__hw_8h_html_a820c08467cb0fc69af91e8747bf52199"><div class="ttname"><a href="xtrafgen__hw_8h.html#a820c08467cb0fc69af91e8747bf52199">XTG_STATIC_CNTL_STEN_MASK</a></div><div class="ttdeci">#define XTG_STATIC_CNTL_STEN_MASK</div><div class="ttdoc">Static enable Mask. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:290</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_ac6e57b26c1f5674deb7c571dc319bf9e"><div class="ttname"><a href="xtrafgen__hw_8h.html#ac6e57b26c1f5674deb7c571dc319bf9e">XTrafGen_WriteReg</a></div><div class="ttdeci">#define XTrafGen_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">XTrafGen_WriteReg, writes Data to the register specified by RegOffset. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:424</div></div>
<div class="ttc" id="group__trafgen__v3__2_html_gafee2ca23e3fc2ed4964740ba69dde023"><div class="ttname"><a href="group__trafgen__v3__2.html#gafee2ca23e3fc2ed4964740ba69dde023">XTG_STATIC_CNTL_OFFSET</a></div><div class="ttdeci">#define XTG_STATIC_CNTL_OFFSET</div><div class="ttdoc">Static Mode Register Descrptions. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:99</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_affb7c95abd8cad50d7efa83f94ea3344"><div class="ttname"><a href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a></div><div class="ttdeci">#define XTrafGen_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...</div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:404</div></div>
</div><!-- fragment -->
<p>XTrafGen_StaticEnable enable the traffic genration when the core is configured Static Mode. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Axi TrafGen instance to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__trafgen__v3__2.html#ga21218c919ca08e948a557334a8f1ba95" title="XTrafGen_StaticEnable enable the traffic genration when the core is configured Static Mode...">XTrafGen_StaticEnable(XTrafGen *InstancePtr)</a> </dd></dl>

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<a class="anchor" id="ga37b20b8af9dbdef32b778e28b28beebb"></a>
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      <table class="memname">
        <tr>
          <td class="memname">#define XTrafGen_StaticVersion</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">((<a class="code" href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress,           \</div>
<div class="line">                <a class="code" href="group__trafgen__v3__2.html#gafee2ca23e3fc2ed4964740ba69dde023">XTG_STATIC_CNTL_OFFSET</a>) &amp; <a class="code" href="xtrafgen__hw_8h.html#a2f470f08ec693fff5af6c5109f1b3ffc">XTG_STATIC_CNTL_VER_MASK</a>) &gt;&gt;  \</div>
<div class="line">                <a class="code" href="xtrafgen__hw_8h.html#a128106d0d3435137e96192b0386eeec4">XTG_STATIC_CNTL_VER_SHIFT</a> )</div>
<div class="ttc" id="xtrafgen__hw_8h_html_a2f470f08ec693fff5af6c5109f1b3ffc"><div class="ttname"><a href="xtrafgen__hw_8h.html#a2f470f08ec693fff5af6c5109f1b3ffc">XTG_STATIC_CNTL_VER_MASK</a></div><div class="ttdeci">#define XTG_STATIC_CNTL_VER_MASK</div><div class="ttdoc">Version Mask. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:285</div></div>
<div class="ttc" id="group__trafgen__v3__2_html_gafee2ca23e3fc2ed4964740ba69dde023"><div class="ttname"><a href="group__trafgen__v3__2.html#gafee2ca23e3fc2ed4964740ba69dde023">XTG_STATIC_CNTL_OFFSET</a></div><div class="ttdeci">#define XTG_STATIC_CNTL_OFFSET</div><div class="ttdoc">Static Mode Register Descrptions. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:99</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_a128106d0d3435137e96192b0386eeec4"><div class="ttname"><a href="xtrafgen__hw_8h.html#a128106d0d3435137e96192b0386eeec4">XTG_STATIC_CNTL_VER_SHIFT</a></div><div class="ttdeci">#define XTG_STATIC_CNTL_VER_SHIFT</div><div class="ttdoc">Version Shift. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:284</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_affb7c95abd8cad50d7efa83f94ea3344"><div class="ttname"><a href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a></div><div class="ttdeci">#define XTrafGen_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...</div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:404</div></div>
</div><!-- fragment -->
<p>XTrafGen_StaticVersion returns the version value for the Axi TrafGen When configured in Static Mode. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Axi TrafGen instance to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Static version value.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__trafgen__v3__2.html#ga37b20b8af9dbdef32b778e28b28beebb" title="XTrafGen_StaticVersion returns the version value for the Axi TrafGen When configured in Static Mode...">XTrafGen_StaticVersion(XTrafGen *InstancePtr)</a> </dd></dl>

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          <td class="memname">#define XTrafGen_StreamDisable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="xtrafgen__hw_8h.html#ac6e57b26c1f5674deb7c571dc319bf9e">XTrafGen_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress,   \</div>
<div class="line">                <a class="code" href="group__trafgen__v3__2.html#gadad67dedb6f0b5c0e7aed2e0d62e08eb">XTG_STREAM_CNTL_OFFSET</a>,                         \</div>
<div class="line">                (<a class="code" href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress,    \</div>
<div class="line">                <a class="code" href="group__trafgen__v3__2.html#gadad67dedb6f0b5c0e7aed2e0d62e08eb">XTG_STREAM_CNTL_OFFSET</a>) &amp; <a class="code" href="xtrafgen__hw_8h.html#ad4ac7a7ef3c84748869c001e04d5dade">XTG_STREAM_CNTL_RESET_MASK</a>)))</div>
<div class="ttc" id="xtrafgen__hw_8h_html_ac6e57b26c1f5674deb7c571dc319bf9e"><div class="ttname"><a href="xtrafgen__hw_8h.html#ac6e57b26c1f5674deb7c571dc319bf9e">XTrafGen_WriteReg</a></div><div class="ttdeci">#define XTrafGen_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">XTrafGen_WriteReg, writes Data to the register specified by RegOffset. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:424</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_ad4ac7a7ef3c84748869c001e04d5dade"><div class="ttname"><a href="xtrafgen__hw_8h.html#ad4ac7a7ef3c84748869c001e04d5dade">XTG_STREAM_CNTL_RESET_MASK</a></div><div class="ttdeci">#define XTG_STREAM_CNTL_RESET_MASK</div><div class="ttdoc">Streaming Disable Mask. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:247</div></div>
<div class="ttc" id="group__trafgen__v3__2_html_gadad67dedb6f0b5c0e7aed2e0d62e08eb"><div class="ttname"><a href="group__trafgen__v3__2.html#gadad67dedb6f0b5c0e7aed2e0d62e08eb">XTG_STREAM_CNTL_OFFSET</a></div><div class="ttdeci">#define XTG_STREAM_CNTL_OFFSET</div><div class="ttdoc">Streaming Control. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:92</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_affb7c95abd8cad50d7efa83f94ea3344"><div class="ttname"><a href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a></div><div class="ttdeci">#define XTrafGen_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...</div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:404</div></div>
</div><!-- fragment -->
<p>XTrafGen_StreamDisable Disable the traffic genration on the Axi TrafGen When core is configured in Streaming Mode. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Axi TrafGen instance to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__trafgen__v3__2.html#ga9254cbaa150c31ba61e141e3cdc9a4c7" title="XTrafGen_StreamDisable Disable the traffic genration on the Axi TrafGen When core is configured in St...">XTrafGen_StreamDisable(XTrafGen *InstancePtr)</a> </dd></dl>

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<a class="anchor" id="gaadc216c9d0077b5906e2b07029b8877a"></a>
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      <table class="memname">
        <tr>
          <td class="memname">#define XTrafGen_StreamEnable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="xtrafgen__hw_8h.html#ac6e57b26c1f5674deb7c571dc319bf9e">XTrafGen_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress,           \</div>
<div class="line">                <a class="code" href="group__trafgen__v3__2.html#gadad67dedb6f0b5c0e7aed2e0d62e08eb">XTG_STREAM_CNTL_OFFSET</a>,                                 \</div>
<div class="line">                (<a class="code" href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress,    \</div>
<div class="line">                <a class="code" href="group__trafgen__v3__2.html#gadad67dedb6f0b5c0e7aed2e0d62e08eb">XTG_STREAM_CNTL_OFFSET</a>) | <a class="code" href="xtrafgen__hw_8h.html#a96e6916449a1ded46ea7882b67d2d732">XTG_STREAM_CNTL_STEN_MASK</a>)))</div>
<div class="ttc" id="xtrafgen__hw_8h_html_ac6e57b26c1f5674deb7c571dc319bf9e"><div class="ttname"><a href="xtrafgen__hw_8h.html#ac6e57b26c1f5674deb7c571dc319bf9e">XTrafGen_WriteReg</a></div><div class="ttdeci">#define XTrafGen_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">XTrafGen_WriteReg, writes Data to the register specified by RegOffset. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:424</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_a96e6916449a1ded46ea7882b67d2d732"><div class="ttname"><a href="xtrafgen__hw_8h.html#a96e6916449a1ded46ea7882b67d2d732">XTG_STREAM_CNTL_STEN_MASK</a></div><div class="ttdeci">#define XTG_STREAM_CNTL_STEN_MASK</div><div class="ttdoc">Streaming Enable Mask. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:246</div></div>
<div class="ttc" id="group__trafgen__v3__2_html_gadad67dedb6f0b5c0e7aed2e0d62e08eb"><div class="ttname"><a href="group__trafgen__v3__2.html#gadad67dedb6f0b5c0e7aed2e0d62e08eb">XTG_STREAM_CNTL_OFFSET</a></div><div class="ttdeci">#define XTG_STREAM_CNTL_OFFSET</div><div class="ttdoc">Streaming Control. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:92</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_affb7c95abd8cad50d7efa83f94ea3344"><div class="ttname"><a href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a></div><div class="ttdeci">#define XTrafGen_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...</div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:404</div></div>
</div><!-- fragment -->
<p>XTrafGen_StreamEnable enable the traffic genration on the Axi TrafGen When the core is configured in Streaming Mode. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Axi TrafGen instance to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__trafgen__v3__2.html#gaadc216c9d0077b5906e2b07029b8877a" title="XTrafGen_StreamEnable enable the traffic genration on the Axi TrafGen When the core is configured in ...">XTrafGen_StreamEnable(XTrafGen *InstancePtr)</a> </dd></dl>

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      <table class="memname">
        <tr>
          <td class="memname">#define XTrafGen_StreamVersion</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">((<a class="code" href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress,   \</div>
<div class="line">                <a class="code" href="group__trafgen__v3__2.html#gadad67dedb6f0b5c0e7aed2e0d62e08eb">XTG_STREAM_CNTL_OFFSET</a>) &amp; <a class="code" href="xtrafgen__hw_8h.html#a33aba05b605e1929b2045d76228f04f5">XTG_STREAM_CNTL_VER_MASK</a>) \</div>
<div class="line">                &gt;&gt; <a class="code" href="xtrafgen__hw_8h.html#a49c88fdab76f14bbf070eebcedc16ef1">XTG_STREAM_CNTL_VER_SHIFT</a> )</div>
<div class="ttc" id="xtrafgen__hw_8h_html_a33aba05b605e1929b2045d76228f04f5"><div class="ttname"><a href="xtrafgen__hw_8h.html#a33aba05b605e1929b2045d76228f04f5">XTG_STREAM_CNTL_VER_MASK</a></div><div class="ttdeci">#define XTG_STREAM_CNTL_VER_MASK</div><div class="ttdoc">Version Mask. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:241</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_a49c88fdab76f14bbf070eebcedc16ef1"><div class="ttname"><a href="xtrafgen__hw_8h.html#a49c88fdab76f14bbf070eebcedc16ef1">XTG_STREAM_CNTL_VER_SHIFT</a></div><div class="ttdeci">#define XTG_STREAM_CNTL_VER_SHIFT</div><div class="ttdoc">Version Shift. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:240</div></div>
<div class="ttc" id="group__trafgen__v3__2_html_gadad67dedb6f0b5c0e7aed2e0d62e08eb"><div class="ttname"><a href="group__trafgen__v3__2.html#gadad67dedb6f0b5c0e7aed2e0d62e08eb">XTG_STREAM_CNTL_OFFSET</a></div><div class="ttdeci">#define XTG_STREAM_CNTL_OFFSET</div><div class="ttdoc">Streaming Control. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:92</div></div>
<div class="ttc" id="xtrafgen__hw_8h_html_affb7c95abd8cad50d7efa83f94ea3344"><div class="ttname"><a href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a></div><div class="ttdeci">#define XTrafGen_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...</div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:404</div></div>
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<p>XTrafGen_StreamVersion returns the version value for the Axi TrafGen When configured in Streaming Mode. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Axi TrafGen instance to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Streaming Version Value.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u8 <a class="el" href="group__trafgen__v3__2.html#ga97bb49960ada1e396862580a5e41755e" title="XTrafGen_StreamVersion returns the version value for the Axi TrafGen When configured in Streaming Mod...">XTrafGen_StreamVersion(XTrafGen *InstancePtr)</a> </dd></dl>

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          <td class="memname">#define XTrafGen_WriteSlaveControlReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Value&#160;</td>
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          <td></td>
          <td>)</td>
          <td></td><td></td>
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<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xtrafgen__hw_8h.html#ac6e57b26c1f5674deb7c571dc319bf9e">XTrafGen_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress,    \</div>
<div class="line">                <a class="code" href="group__trafgen__v3__2.html#ga16ab165b5d7fd7c84206606b1bc2dcfa">XTG_SCNTL_OFFSET</a>, Value)</div>
<div class="ttc" id="xtrafgen__hw_8h_html_ac6e57b26c1f5674deb7c571dc319bf9e"><div class="ttname"><a href="xtrafgen__hw_8h.html#ac6e57b26c1f5674deb7c571dc319bf9e">XTrafGen_WriteReg</a></div><div class="ttdeci">#define XTrafGen_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">XTrafGen_WriteReg, writes Data to the register specified by RegOffset. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:424</div></div>
<div class="ttc" id="group__trafgen__v3__2_html_ga16ab165b5d7fd7c84206606b1bc2dcfa"><div class="ttname"><a href="group__trafgen__v3__2.html#ga16ab165b5d7fd7c84206606b1bc2dcfa">XTG_SCNTL_OFFSET</a></div><div class="ttdeci">#define XTG_SCNTL_OFFSET</div><div class="ttdoc">Slave Control. </div><div class="ttdef"><b>Definition:</b> xtrafgen_hw.h:87</div></div>
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<p>XTrafGen_WriteSlaveControlReg enables control bits of Slave Control Register. </p>
<p>This API will write the value passed from the user.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Axi TrafGen instance to be worked on. </td></tr>
    <tr><td class="paramname">Value</td><td>is the Slave Control Register value to set</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void XTrafGen_WriteSlaveControlReg(<a class="el" href="struct_x_traf_gen.html" title="The XTrafGen driver instance data. ">XTrafGen</a> *InstancePtr, u32 Value) </dd></dl>

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<h2 class="groupheader">Typedef Documentation</h2>
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<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>

<p>The <a class="el" href="struct_x_traf_gen.html" title="The XTrafGen driver instance data. ">XTrafGen</a> driver instance data. </p>
<p>An instance must be allocated for each Traffic Generator device in use. </p>

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<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>

<p>Command structure exposed to user. </p>
<p>This structure should be updated by user with required configuration </p>

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<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>

<p>Command Entry structure. </p>
<p>This structure denotes each entry of 256 commands. </p>

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<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>

<p>Command Information Structure. </p>
<p>This structure is maintained by the driver </p>

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<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>

<p>The configuration structure for Traffic Generator device. </p>
<p>This structure passes the hardware building information to the driver </p>

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          <td class="memname">typedef struct <a class="el" href="struct_x_traf_gen___c_ram_cmd.html">XTrafGen_CRamCmd</a>  <a class="el" href="struct_x_traf_gen___c_ram_cmd.html">XTrafGen_CRamCmd</a></td>
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<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>

<p>Command Ram word fields. </p>

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<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>

<p>Parameter Ram word fields. </p>

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<h2 class="groupheader">Function Documentation</h2>
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          <td class="memname">void XTrafGen_AccessMasterRam </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_traf_gen.html">XTrafGen</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Offset</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">int&#160;</td>
          <td class="paramname"><em>Length</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>RdWrFlag</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32 *&#160;</td>
          <td class="paramname"><em>Data</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
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<p><code>#include &lt;<a class="el" href="xtrafgen_8c.html">xtrafgen.c</a>&gt;</code></p>

<p>Write or Read Master RAM. </p>
<p>The MSTRAM has 8 KB of internal RAM used for the following:</p><ul>
<li>Take data from this RAM for write transactions</li>
<li>Store data to this RAM for read transaction</li>
</ul>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Axi TrafGen instance to be worked on. </td></tr>
    <tr><td class="paramname">Offset</td><td>is the offset value in Master RAM. </td></tr>
    <tr><td class="paramname">Length</td><td>is the size of data to write/read. </td></tr>
    <tr><td class="paramname">RdWrFlag</td><td>specifies whether to write or read </td></tr>
    <tr><td class="paramname">Data</td><td>is the pointer to array which contains data to write or reads data into. </td></tr>
  </table>
  </dd>
</dl>

<p>References <a class="el" href="struct_x_traf_gen___config.html#ac47f34b47fc9fb39c04ac7a57ac58d48">XTrafGen_Config::BaseAddress</a>, <a class="el" href="struct_x_traf_gen.html#a201c38f1c1aee1167972954d71b2e013">XTrafGen::Config</a>, <a class="el" href="group__trafgen__v3__2.html#ga255c930454b0fb1a4a1b9dbe7c704692">XTG_MASTER_RAM_SIZE</a>, <a class="el" href="group__trafgen__v3__2.html#ga8a676092267b72a3e5ad91718b914ecf">XTG_WRITE</a>, <a class="el" href="xtrafgen__hw_8h.html#a60ceec5d839e8a8f1cdda74c93c425b8">XTrafGen_ReadMasterRam</a>, and <a class="el" href="xtrafgen__hw_8h.html#a8fe8b5ce12fefb6bba6acee1b89cb2a7">XTrafGen_WriteMasterRam</a>.</p>

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          <td class="memname">int XTrafGen_AddCommand </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_traf_gen.html">XTrafGen</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="struct_x_traf_gen___cmd.html">XTrafGen_Cmd</a> *&#160;</td>
          <td class="paramname"><em>CmdPtr</em>&#160;</td>
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          <td>)</td>
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<p><code>#include &lt;<a class="el" href="xtrafgen_8c.html">xtrafgen.c</a>&gt;</code></p>

<p>Add a command to the software list of commands. </p>
<p>This function prepares the four Command Words and one Parameter Word from the Command structure passed from the user application. It then adds to a list of commands (maintained in the software). Both CMDRAM and PARAMRAM are divided into two regions, one for reads and one for writes. Each region can hold 256 commands with each entry containing four Command RAM words and one Parameter RAM word.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Axi TrafGen instance to be worked on. </td></tr>
    <tr><td class="paramname">CmdPtr</td><td>is a pointer to Command structure.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if successful</li>
<li>XST_FAILURE if reached max number of command entries </li>
</ul>
</dd></dl>

<p>References <a class="el" href="struct_x_traf_gen___cmd_info.html#a8539c121534f1c06cc7e8b9134161a4e">XTrafGen_CmdInfo::CmdEntry</a>, <a class="el" href="struct_x_traf_gen___cmd_entry.html#a4431358883728fa489017ff778edaf05">XTrafGen_CmdEntry::CmdWords</a>, <a class="el" href="struct_x_traf_gen___cmd.html#ad9231ba1f718b9a9511f1a3ea863bca1">XTrafGen_Cmd::CRamCmd</a>, <a class="el" href="struct_x_traf_gen___cmd_info.html#acdf227f8d8c37fa5cdec0d8e0b8a6f97">XTrafGen_CmdInfo::LastRdValidIndex</a>, <a class="el" href="struct_x_traf_gen___cmd_info.html#a205e3808435db7d2f79be395fabc7083">XTrafGen_CmdInfo::LastWrValidIndex</a>, <a class="el" href="group__trafgen__v3__2.html#gaefe8b2fd0fb990e5cfa429c8b49b3162">MAX_NUM_ENTRIES</a>, <a class="el" href="struct_x_traf_gen___cmd_entry.html#ac6e17477fa216e9c9216591b36fe0feb">XTrafGen_CmdEntry::ParamWord</a>, <a class="el" href="struct_x_traf_gen___cmd_info.html#a8caa1f7535069edf212909b1ba944331">XTrafGen_CmdInfo::RdIndex</a>, <a class="el" href="struct_x_traf_gen___cmd_info.html#a56f23c33a284db97c318415ce35dd267">XTrafGen_CmdInfo::RdIndexEnd</a>, <a class="el" href="struct_x_traf_gen___cmd.html#a6c452068b7aac042b11056897c6da2c7">XTrafGen_Cmd::RdWrFlag</a>, <a class="el" href="struct_x_traf_gen___c_ram_cmd.html#a197e871656f2931f5c4c0e6c366ed7cb">XTrafGen_CRamCmd::ValidCmd</a>, <a class="el" href="struct_x_traf_gen___cmd_info.html#ac47a05425af17e0d45181666230c9bf3">XTrafGen_CmdInfo::WrIndex</a>, <a class="el" href="struct_x_traf_gen___cmd_info.html#a2bf6bf32479362d7c22f20bd916003e4">XTrafGen_CmdInfo::WrIndexEnd</a>, <a class="el" href="group__trafgen__v3__2.html#ga8a676092267b72a3e5ad91718b914ecf">XTG_WRITE</a>, and <a class="el" href="group__trafgen__v3__2.html#gaa852fb64cd7119a1feeb5715a794d79d">XTrafGen_GetCmdInfo</a>.</p>

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          <td>(</td>
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          <td class="paramname"><em>InstancePtr</em>, </td>
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          <td></td>
          <td class="paramtype"><a class="el" href="struct_x_traf_gen___config.html">XTrafGen_Config</a> *&#160;</td>
          <td class="paramname"><em>Config</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">UINTPTR&#160;</td>
          <td class="paramname"><em>EffectiveAddress</em>&#160;</td>
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          <td>)</td>
          <td></td><td></td>
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<p><code>#include &lt;<a class="el" href="xtrafgen_8c.html">xtrafgen.c</a>&gt;</code></p>

<p>This function initializes a AXI Traffic Generator device. </p>
<p>This function must be called prior to using a AXI Traffic Generator Device. Initializing a engine includes setting up the register base address, setting up the instance data, and ensuring the hardware is in a quiescent state.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Axi Traffic Generator instance to be worked on. </td></tr>
    <tr><td class="paramname">CfgPtr</td><td>references the structure holding the hardware configuration for the Axi Traffic Generator core to initialize. </td></tr>
    <tr><td class="paramname">EffectiveAddr</td><td>is the device base address in the virtual memory address space. The caller is responsible for keeping the address mapping from EffectiveAddr to the device physical base address unchanged once this function is invoked. Unexpected errors may occur if the address mapping changes after this function is called. If address translation is not used, use Config-&gt;BaseAddress for this parameters, passing the physical address instead.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS for successful initialization</li>
<li>XST_INVALID_PARAM if pointer to the configuration structure is NULL </li>
</ul>
</dd></dl>

<p>References <a class="el" href="struct_x_traf_gen___config.html#ab2066859b864fc23e9f469f26d3feb36">XTrafGen_Config::AddressWidth</a>, <a class="el" href="struct_x_traf_gen___config.html#ac47f34b47fc9fb39c04ac7a57ac58d48">XTrafGen_Config::BaseAddress</a>, <a class="el" href="struct_x_traf_gen___config.html#a8c2ea6103b3622bd14ca11da53a52ab0">XTrafGen_Config::BusType</a>, <a class="el" href="struct_x_traf_gen.html#a402442f79d61e7de11b82b94ebbb068a">XTrafGen::CmdInfo</a>, <a class="el" href="struct_x_traf_gen.html#a201c38f1c1aee1167972954d71b2e013">XTrafGen::Config</a>, <a class="el" href="struct_x_traf_gen___config.html#a4dd60afb185aa1eee90bfcecc16ca125">XTrafGen_Config::DeviceId</a>, <a class="el" href="struct_x_traf_gen___cmd_info.html#acdf227f8d8c37fa5cdec0d8e0b8a6f97">XTrafGen_CmdInfo::LastRdValidIndex</a>, <a class="el" href="struct_x_traf_gen___cmd_info.html#a205e3808435db7d2f79be395fabc7083">XTrafGen_CmdInfo::LastWrValidIndex</a>, <a class="el" href="struct_x_traf_gen.html#ad63beb04ce3dcb61eb0757381e24164f">XTrafGen::MasterWidth</a>, <a class="el" href="struct_x_traf_gen___config.html#af5beef5de3c1bbb73fb81c0e56ddced7">XTrafGen_Config::Mode</a>, <a class="el" href="struct_x_traf_gen___config.html#a54e94b76d7c873cfeedb79f58756191e">XTrafGen_Config::ModeType</a>, <a class="el" href="struct_x_traf_gen.html#af67f6122abede0916eb19b1fcbb33794">XTrafGen::OperatingMode</a>, <a class="el" href="struct_x_traf_gen.html#a60c7caaa1b4c37932baa882d39bac5af">XTrafGen::SlaveWidth</a>, <a class="el" href="xtrafgen__hw_8h.html#a73aac9edd6e776525f4e44865ed7e481">XTG_CFG_STS_MBASIC_MASK</a>, <a class="el" href="xtrafgen__hw_8h.html#a1816012cab8ec1b93b06d20dde1e0128">XTG_CFG_STS_MFULL_MASK</a>, <a class="el" href="xtrafgen__hw_8h.html#a7387f793b21568825291b8ae05e9a8dc">XTG_CFG_STS_MWIDTH_MASK</a>, <a class="el" href="xtrafgen__hw_8h.html#a43010263c928054845a6e4da818c5cb6">XTG_CFG_STS_MWIDTH_SHIFT</a>, <a class="el" href="xtrafgen__hw_8h.html#a641638626484a52b81fbbf8f30bd45dc">XTG_CFG_STS_SWIDTH_MASK</a>, <a class="el" href="xtrafgen__hw_8h.html#ab8521be4a5dc1628cb3a3afe87298843">XTG_CFG_STS_SWIDTH_SHIFT</a>, <a class="el" href="group__trafgen__v3__2.html#ga4b6bd2e6c7f45de76c7fb1241c364347">XTG_MODE_BASIC</a>, <a class="el" href="group__trafgen__v3__2.html#ga80fcb2c884f7369ddbaffc1e51bba9ce">XTG_MODE_FULL</a>, <a class="el" href="group__trafgen__v3__2.html#ga15499801ae618925ac45a3a55807e1d6">XTG_MODE_STATIC</a>, <a class="el" href="group__trafgen__v3__2.html#gaf22b2f8af4980fac9d5faaf3001ab0f0">XTG_MODE_STREAMING</a>, <a class="el" href="group__trafgen__v3__2.html#ga3d8b67e1ec714d525de17946ec19ad49">XTG_MODE_SYS_INIT</a>, and <a class="el" href="group__trafgen__v3__2.html#gad072536408b0e73e38978c57e0002c79">XTrafGen_ReadConfigStatus</a>.</p>

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          <td class="memname">int XTrafGen_EraseAllCommands </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_traf_gen.html">XTrafGen</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
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<p><code>#include &lt;<a class="el" href="xtrafgen_8c.html">xtrafgen.c</a>&gt;</code></p>

<p>Erase all Command Entry values. </p>
<p>This function erases all the 256 entries of both write and read regions with each entry containing four command words and parameter word.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Axi TrafGen instance to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if successful<ul>
<li>XST_FAILURE if programming internal RAMs failed </li>
</ul>
</li>
</ul>
</dd></dl>

<p>References <a class="el" href="struct_x_traf_gen___cmd_info.html#a8539c121534f1c06cc7e8b9134161a4e">XTrafGen_CmdInfo::CmdEntry</a>, <a class="el" href="struct_x_traf_gen___cmd_info.html#acdf227f8d8c37fa5cdec0d8e0b8a6f97">XTrafGen_CmdInfo::LastRdValidIndex</a>, <a class="el" href="struct_x_traf_gen___cmd_info.html#a205e3808435db7d2f79be395fabc7083">XTrafGen_CmdInfo::LastWrValidIndex</a>, <a class="el" href="group__trafgen__v3__2.html#gaefe8b2fd0fb990e5cfa429c8b49b3162">MAX_NUM_ENTRIES</a>, <a class="el" href="group__trafgen__v3__2.html#ga622293b32ccc06f19e7f568ba80a2390">NUM_BLOCKS</a>, <a class="el" href="struct_x_traf_gen___cmd_info.html#a8caa1f7535069edf212909b1ba944331">XTrafGen_CmdInfo::RdIndex</a>, <a class="el" href="struct_x_traf_gen___cmd_info.html#a56f23c33a284db97c318415ce35dd267">XTrafGen_CmdInfo::RdIndexEnd</a>, <a class="el" href="struct_x_traf_gen___cmd_info.html#ac47a05425af17e0d45181666230c9bf3">XTrafGen_CmdInfo::WrIndex</a>, <a class="el" href="struct_x_traf_gen___cmd_info.html#a2bf6bf32479362d7c22f20bd916003e4">XTrafGen_CmdInfo::WrIndexEnd</a>, and <a class="el" href="group__trafgen__v3__2.html#gaa852fb64cd7119a1feeb5715a794d79d">XTrafGen_GetCmdInfo</a>.</p>

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          <td class="memname">int XTrafGen_GetLastValidIndex </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_traf_gen.html">XTrafGen</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
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          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>RdWrFlag</em>&#160;</td>
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          <td></td>
          <td>)</td>
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<p><code>#include &lt;<a class="el" href="xtrafgen_8c.html">xtrafgen.c</a>&gt;</code></p>

<p>Get last Valid Command Index of Write/Read region. </p>
<p>The last valid command index is used to set 'my_depend' and 'other_depend' fields of the Command RAM (Word 2).</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Axi TrafGen instance to be worked on. </td></tr>
    <tr><td class="paramname">RdWrFlag</td><td>specifies a Read or Write Region</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>Last Valid Command Index </li>
</ul>
</dd></dl>

<p>References <a class="el" href="struct_x_traf_gen___cmd_info.html#acdf227f8d8c37fa5cdec0d8e0b8a6f97">XTrafGen_CmdInfo::LastRdValidIndex</a>, <a class="el" href="struct_x_traf_gen___cmd_info.html#a205e3808435db7d2f79be395fabc7083">XTrafGen_CmdInfo::LastWrValidIndex</a>, <a class="el" href="group__trafgen__v3__2.html#ga8a676092267b72a3e5ad91718b914ecf">XTG_WRITE</a>, and <a class="el" href="group__trafgen__v3__2.html#gaa852fb64cd7119a1feeb5715a794d79d">XTrafGen_GetCmdInfo</a>.</p>

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          <td class="memname"><a class="el" href="struct_x_traf_gen___config.html">XTrafGen_Config</a> * XTrafGen_LookupConfig </td>
          <td>(</td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>DeviceId</em></td><td>)</td>
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<p><code>#include &lt;<a class="el" href="xtrafgen_8h.html">xtrafgen.h</a>&gt;</code></p>

<p>Look up the hardware configuration for a device instance. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">DeviceId</td><td>is the unique device ID of the device to lookup for</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The configuration structure for the device. If the device ID is not found,a NULL pointer is returned.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None </dd></dl>

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          <td class="memname">void XTrafGen_PrintCmds </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_traf_gen.html">XTrafGen</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
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<p><code>#include &lt;<a class="el" href="xtrafgen_8c.html">xtrafgen.c</a>&gt;</code></p>

<p>Display Command Entry values. </p>
<p>This function prints all the 256 entries of both write and read regions with each entry containing four command words and parameter word.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Axi TrafGen instance to be worked on. </td></tr>
  </table>
  </dd>
</dl>

<p>References <a class="el" href="struct_x_traf_gen___cmd_info.html#a8539c121534f1c06cc7e8b9134161a4e">XTrafGen_CmdInfo::CmdEntry</a>, <a class="el" href="struct_x_traf_gen___cmd_entry.html#a4431358883728fa489017ff778edaf05">XTrafGen_CmdEntry::CmdWords</a>, <a class="el" href="group__trafgen__v3__2.html#gaefe8b2fd0fb990e5cfa429c8b49b3162">MAX_NUM_ENTRIES</a>, <a class="el" href="struct_x_traf_gen___cmd_entry.html#ac6e17477fa216e9c9216591b36fe0feb">XTrafGen_CmdEntry::ParamWord</a>, and <a class="el" href="group__trafgen__v3__2.html#gaa852fb64cd7119a1feeb5715a794d79d">XTrafGen_GetCmdInfo</a>.</p>

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          <td class="memname">int XTrafGen_WriteCmdsToHw </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_traf_gen.html">XTrafGen</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
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<p><code>#include &lt;<a class="el" href="xtrafgen_8c.html">xtrafgen.c</a>&gt;</code></p>

<p>Write Commands to internal Command and Parameter RAMs. </p>
<p>This function writes all the prepared commands to hardware.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Axi TrafGen instance to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if successful<ul>
<li>XST_FAILURE if programming internal RAMs failed </li>
</ul>
</li>
</ul>
</dd></dl>

<p>References <a class="el" href="group__trafgen__v3__2.html#ga622293b32ccc06f19e7f568ba80a2390">NUM_BLOCKS</a>.</p>

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